Semiconductor Chip Substrate with Multi-Capacitor Footprint
AssigneeATI Technologies ULC
InventorsYue Li, Silqun Leung, Terence Cheung, Sally Yeung, Liane Martinez
Life of this patent
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Abstract
Various methods and apparatus for coupling capacitors to a chip substrate are disclosed. In one aspect, a method of manufacturing is provided that includes forming a mask on a semiconductor chip substrate that has plural conductor pads. The mask has plural openings that expose selected portions of the plural conductor pads. Each of the plural openings has a footprint corresponding to a footprint of a smallest size terminal of a capacitor adapted to be coupled to the semiconductor chip substrate. A conductor material is placed in the plural openings to establish plural capacitor pads.
Claims22
A method of manufacturing, comprising:
- forming a mask on a semiconductor chip substrate having plural conductor pads, the mask having plural openings exposing selected portions of the plural conductor pads, each of the plural openings having a footprint corresponding to a footprint of a smallest size terminal of a capacitor adapted to be coupled to the semiconductor chip substrate;
- and
- placing conductor material in the plural openings to establish plural capacitor pads.
A method of manufacturing, comprising:
- providing a semiconductor chip substrate having plural conductor pads and being adapted to have a semiconductor chip coupled thereto;
- forming a mask on a semiconductor chip substrate having plural conductor pads, the mask having plural openings exposing selected portions of the plural conductor pads, each of the plural openings having a footprint corresponding to a footprint of a smallest size terminal of a capacitor adapted to be coupled to the semiconductor chip substrate;
- placing conductor material in the plural openings to establish plural capacitor pads;
- determining a requisite decoupling capacitance for a combination of the semiconductor chip package and the semiconductor chip;
- and
- coupling plural capacitors to the semiconductor chip substrate, the plural capacitors collectively having the requisite decoupling capacitance, each of the plural capacitors being coupled to at least two of the plural capacitor pads, at least one of the plural capacitors having the smallest size terminal.
An apparatus, comprising:
- a semiconductor chip substrate including plural conductor pads;
- an insulating layer on the semiconductor chip substrate, the insulating layer having plural openings to selected portions of the plural conductor pads, each of the plural openings having a footprint corresponding to a footprint of a smallest size terminal of a capacitor adapted to be coupled to the semiconductor chip substrate;
- and
- plural capacitor pads positioned in corresponding of the plural openings.
An apparatus, comprising:
- a semiconductor chip substrate including a first pair of conductor pads and a second pair of conductor pads, each of the first pair of conductor pads having a first size and each of the second pair of conductor pads having a second size larger than the first size;
- an insulating layer on the semiconductor chip substrate, the insulating layer having a first opening to a first of the first pair of conductor pads and a second opening to the second of the first pair of conductor pads, the insulating layer having at least two openings to selected portions of a first of the second pair of conductor pads and at least two openings to selected portions of the second of the second pair of conductor pads, each of the plural openings having a footprint corresponding to a footprint of a smallest size terminal of a capacitor adapted to be coupled to the semiconductor chip substrate;
- and
- a capacitor pad positioned in the each of the first opening, the second opening, and the at least two openings to each of the second pair of conductor pads.
Dependencies are inferred from the claim text.