Method of manufacturing semiconductor device and the semiconductor device

A method of manufacturing a semiconductor device having an MISFET on a semiconductor substrate, comprising:

• forming a gate insulating film on a semiconductor substrate;
• forming a gate electrode on the gate insulating film;
• implanting ions having a mass equal to or larger than atomic weight of Si into the semiconductor substrate;
• depositing a first metal on the semiconductor substrate;
• reacting the first metal and the semiconductor substrate each other by a first heat treatment to form metal semiconductor compound layers, each being provided on the surface of the semiconductor substrate on one of both sides of the gate electrode;
• depositing a second metal on the metal semiconductor compound layer;
• and
• forming an interface layer by making the second metal segregated at an interface between the metal semiconductor compound layer and the semiconductor substrate by diffusing the second metal through the metal semiconductor compound layer by a second heat treatment,
• wherein in the case where the MISFET is an n-type MISFET, Schottky barrier height for an electron in the interface layer is set to be lower than Schottky barrier height for an electron in the metal semiconductor compound layer, and
• in the case where the MISFET is a p-type MISFET, Schottky barrier height for a hole in the interface layer is set to be lower than Schottky barrier height for a hole in the metal semiconductor compound layer.

A method of manufacturing a semiconductor device having an MISFET of a first conduction type and an MISFET of a second conduction type on a semiconductor substrate, comprising:

• forming a gate insulating film of the MISFET of the first conduction type on a semiconductor substrate;
• forming a gate electrode of the MISFET of the first conduction type on the gate insulating film of the MISFET of the first conduction type;
• forming a gate insulating film of the MISFET of the second conduction type on the semiconductor substrate;
• forming a gate electrode of the MISFET of the second conduction type on the gate insulating film of the MISFET of the second conduction type;
• depositing a first metal on the semiconductor substrate;
• reacting the first metal and the semiconductor substrate each other by a first heat treatment to form metal semiconductor compound layers, each being provided on the surface of the semiconductor substrate on one of both sides of the gate electrode of the MISFET of the first conduction type and on one of both sides of the gate electrode of the MISFET of the second conduction type;
• selectively implanting ions having a mass equal to or larger than atomic weight of Si into the metal semiconductor compound layer in a region in which the MISFET of the first conduction type is formed;
• depositing a second metal on the metal semiconductor compound layer;
• and
• forming an interface layer by making the second metal segregated at an interface between the metal semiconductor compound layer and the semiconductor substrate by diffusing the second metal through the metal semiconductor compound layer in the region in which the MISFET of the first conduction type is formed by a second heat treatment,
• wherein in the case where the MISFET of the first conduction type is an n-type MISFET, Schottky barrier height for an electron in the interface layer is set to be lower than Schottky barrier height for an electron in the metal semiconductor compound layer, and
• in the case where the MISFET of the first conduction type is a p-type MISFET, Schottky barrier height for a hole in the interface layer is set to be lower than Schottky barrier height for a hole in the metal semiconductor compound layer.

A method of manufacturing a semiconductor device having an MISFET of a first conduction type and an MISFET of a second conduction type in a semiconductor substrate, comprising:

• forming a gate insulating film of the MISFET of the first conduction type on a semiconductor substrate;
• forming a gate electrode of the MISFET of the first conduction type on the gate insulating film of the MISFET of the first conduction type;
• forming a gate insulating film of the MISFET of the second conduction type on the semiconductor substrate;
• forming a gate electrode of the MISFET of the second conduction type on the gate insulating film of the MISFET of the second conduction type;
• selectively implanting ions having a mass equal to or larger than atomic weight of Si into the semiconductor substrate in a region in which the MISFET of the first conduction type is formed;
• depositing a first metal on the semiconductor substrate;
• reacting the first metal and the semiconductor substrate each other by a first heat treatment to form metal semiconductor compound layers, each being provided on the surface of the semiconductor substrate on one of both sides of the gate electrode of the MISFET of the first conduction type and on one of both sides of the gate electrode of the MISFET of the second conduction type;
• depositing a second metal on the metal semiconductor compound layer;
• and
• forming an interface layer by making the second metal segregated at an interface between the metal semiconductor compound layer and the semiconductor substrate by diffusing the second metal through the metal semiconductor compound layer in the region in which the MISFET of the first conduction type is formed by a second heat treatment,
• wherein in the case where the MISFET of the first conduction type is an n-type MISFET, Schottky barrier height for an electron in the interface layer is set to be lower than Schottky barrier height for an electron in the metal semiconductor compound layer, and
• in the case where the MISFET of the first conduction type is a p-type MISFET, Schottky barrier height for a hole in the interface layer is set to be lower than Schottky barrier height for a hole in the metal semiconductor compound layer.

A semiconductor device having an MISFET comprising:

• a channel region formed in a semiconductor substrate;
• a gate insulating film formed on the surface of the channel region;
• a gate electrode formed on the gate insulating film;
• and
• a source-drain electrode formed on both sides of the channel region,
• wherein the source-drain electrode is formed by a metal semiconductor compound layer containing a first metal,
• an interface layer containing a second metal is formed at an interface between the semiconductor substrate and the metal semiconductor compound layer,
• in a section of an arbitrary 1 μm×1 μm area of the metal semiconductor compound layer, ¾ or more of the area is occupied by crystal grains of a grain size of 100 nm or less,
• in the case where the MISFET is an n-type MISFET, Schottky barrier height for an electron in the interface layer is lower than that of Schottky barrier height for an electron in the metal semiconductor compound layer, and
• in the case where the MISFET is a p-type MISFET, Schottky barrier height for a hole in the interface layer is lower than that Schottky barrier height for a hole in the metal semiconductor compound layer.