High-k dielectric and metal gate stack with minimal overlap with isolation region and related methods

A method comprising:

• providing a substrate having a first active region defined therein by an oxide isolation region and a second active region defined therein by an oxide isolation region;
• forming a first high dielectric constant (high-k) dielectric and metal gate stack over the first active region in the substrate, the first high-k dielectric and metal gate stack overlapping the oxide isolation region by less than 200 nanometers;
• forming a second high-k dielectric and metal gate stack over the second active region adjacent to the first high-k dielectric and metal gate stack, the second high-k dielectric and metal gate stack overlapping the oxide isolation region by less than approximately 200 nanometers;
• depositing a polysilicon over the first and second high-k dielectric and metal gate stacks;
• and
• patterning the first and second high-k dielectric and metal gate stack to form a pair of gate electrodes.