Field-effect transistor including localized halo ion regions, and semiconductor memory, memory card, and system including the same
AssigneeSamsung Electronics Co., Ltd.
InventorsHyuck-Chai JUNG, June-Hee LIM
Life of this patent
Estimating the term…
Abstract
A field-effect transistor including localized halo ion regions that can optimize HEIP characteristics and GIDL characteristics. The field-effect transistor includes a substrate, an active region, a gate structure, and halo ion regions. The active region includes source/drain regions and a channel region formed at a partial region in the substrate. The gate structure electrically contacts the active region. The halo ion regions are locally formed adjacent to both end portions of the source/drain regions in the substrate.
Claims20
A field-effect transistor comprising:
- a substrate;
- an active region comprising source/drain regions and a channel region formed at a partial region in the substrate, the source region having an end portion and the drain region having an end portion;
- a gate structure electrically contacting the active region;
- and
- halo ion regions locally formed adjacent to both end portions of the source/drain regions in the substrate.
A semiconductor memory comprising:
- a substrate;
- a plurality of active regions each comprising source/drain regions and a channel region formed at a partial region in the substrate, each source region having an end portion and each drain region having an end portion;
- a plurality of field-effect transistors respectively having a plurality of gate structures that respectively contact the active regions electrically,
- the field-effect transistors comprising:
- one or more first field-effect transistors each comprising first halo ion regions that are locally formed adjacent to both end portions of the first source/drain regions in the substrate;
- and
- one or more second field-effect transistors each comprising second halo ion regions that are adjacent to the second source/drain regions in the substrate and are continuously formed along the longitudinal direction of the second source/drain regions.
A memory card comprising:
- a memory comprising a field-effect transistor, wherein the field-effect transistor comprises a substrate, an active region comprising source/drain regions each having an end portion and a channel region formed at a partial region in the substrate, a gate structure electrically contacting the active region, and halo ion regions locally formed adjacent to both end portions of the source/drain regions in the substrate, and wherein the source region includes an end portion and the drain portion includes an end portion;
- and
- a controller configured to control the memory and to communicate data with the memory.
A system comprising:
- a memory comprising a field-effect transistor, wherein the field-effect transistor comprises a substrate, an active region comprising source/drain regions each having an end portion and a channel region formed at a partial region in the substrate, a gate structure electrically contacting the active region, and halo ion regions locally formed adjacent to both end portions of the source/drain regions in the substrate;
- a processor configured to communicate with the memory through a bus;
- and
- an input/output apparatus configured to communicate with the bus.
Dependencies are inferred from the claim text.