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US 2009/0152633 A1Published application
Semiconductor device
AssigneeSeiko Instruments Inc.
InventorsHiroaki Takasu, Sukehiro Yamamoto
Life of this patent
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Abstract
In a semiconductor device including, between an external connection terminal and an internal circuit region, an NMOS transistor for ESD protection having a gate potential fixed to a ground potential, the external connection terminal is formed above a drain region of the NMOS transistor for ESD protection, and the drain region is surrounded by a source region through a channel region. Further, the drain region has a shape with rounded corners in plan view.
Claims6
A semiconductor device, comprising:
- a silicon substrate;
- an external connection terminal disposed on the silicon substrate;
- an internal circuit region disposed on the silicon substrate;
- an NMOS transistor for electrostatic discharge protection provided between the external connection terminal and the internal circuit region to protect an internal element formed on the internal circuit region from an electrostatic discharge breakdown;
- a first wiring connecting the external connection terminal and the NMOS transistor for electrostatic discharge protection;
- and
- a second wiring connecting the NMOS transistor for electrostatic discharge protection and the internal circuit region,
- the NMOS transistor for electrostatic discharge protection having a gate whose potential is fixed to a ground potential, and
- the external connection terminal being formed only above a drain region of the NMOS transistor for electrostatic discharge protection.
6 more elements
Dependencies are inferred from the claim text.