Semiconductor device and method for forming the same

A semiconductor device comprising:

• a n-type thin film transistor comprising:
• a first semiconductor layer formed on an insulating surface;
• a pair of first impurity regions formed in the first semiconductor layer;
• a pair of second impurity regions formed between the pair of first impurity regions;
• a first channel region formed between the pair of second impurity regions;
• a pair of metal silicide regions formed on the pair of first impurity regions;
• a first gate insulating film formed over the first semiconductor layer;
• a first gate electrode formed over the first gate insulating film;
• a pair of first side walls adjacent to the first gate electrode;
• a first insulating film provided between the first gate electrode and the pair of first side walls;
• a second insulating film formed over the first gate electrode, the first insulating film and the pair of first side walls;
• and
• a first electrode formed over the second insulating film and electrically connected to one of the pair of first metal silicide regions,
• a p-type thin film transistor comprising:
• a second semiconductor layer formed on the insulating surface;
• a pair of third impurity regions formed in the second semiconductor layer;
• a pair of fourth impurity regions formed between the pair of third impurity regions;
• a second channel region formed between the pair of fourth impurity regions;
• a pair of second metal silicide regions formed on the pair of third impurity regions;
• a second gate insulating film formed over the second semiconductor layer;
• a second gate electrode formed over the second gate insulating film;
• a pair of second side walls adjacent to the second gate electrode;
• a third insulating film provided between the second gate electrode and the pair of second side walls;
• a fourth insulating film formed over the second gate electrode, the third insulating film and the pair of second side walls;
• and
• an second electrode formed over the fourth insulating film and electrically connected to one of the pair of second metal silicide regions,
• wherein the first gate insulating film and the second gate insulating film are identical,
• wherein the first gate electrode and the second gate electrode are identical,
• wherein the second insulating film and the fourth insulating film are identical,
• wherein the pair of first side walls is contact with end portions of the first gate insulating film, and
• wherein a maximum width of each of the pair of second side walls is larger than a width of the third insulating film between the second gate electrode and each of the pair of second side walls in a second channel direction.