Semiconductor memory device having a floating body capacitor and method of manufacturing the same
AssigneeHynix Semiconductor Inc.
InventorJong-Su Kim
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device having a floating body capacitor. The semiconductor memory device can perform a memory operation using the floating body capacitor. The semiconductor memory device includes an SOI substrate having a staked structure in which a base substrate having a conducting surface, a buried insulating layer and a device-forming layer are staked, a transistor formed in a portion of the device-forming layer, having a gate, a source region and a drain region, and a capacitor formed by the buried insulating layer, the conducting surface of the base substrate, and accumulated holes generated in the device-forming layer when the transistor is driven.
Claims16
A semiconductor memory device comprising:
- a semiconductor substrate;
- a transistor formed in a portion of the semiconductor substrate, having a gate, a source region and a drain region;
- and
- a capacitor buried in the semiconductor substrate and electrically connected to the semiconductor substrate, wherein the capacitor carries out a memory operation when the transistor is driven.
A semiconductor memory device comprising:
- an SOI substrate having a staked structure in which a base substrate having a conducting surface, a buried insulating layer and a device-forming layer are staked;
- a transistor formed in a portion of the device-forming layer, having a gate, a source region and a drain region;
- and
- a capacitor formed by the buried insulating layer, the conducting surface of the base substrate, and accumulated holes generated in the device-forming layer when the transistor is driven.
A method for forming a semiconductor memory device comprising:
- providing an SOI substrate, wherein the SOI substrate includes a base substrate having a conducting surface, a buried insulating layer and a device-forming layer;
- forming a transistor having a gate, a source region and a drain region on the SOI substrate;
- and
- forming a contact plug in contact with the conducting surface of the base substrate, wherein an adjustable bias voltage is applied to the contact plug.
Dependencies are inferred from the claim text.