Semiconductor devices and method of testing same

A semiconductor device comprising a pair of row wires arranged in a first layer to be elongated in a row direction, and a column wire formed in a column direction so as to overlap an end of one of said pair of row wires, wherein:

• in said pair of row wires,
• one row wire has a first end in the row direction connected to a first conductor, and a second end connected to said column wire through a via to be set to a first potential;
• and
• the other row wire has a second end in the row direction connected to a second conductor, and said row wire is set to a second potential.

A semiconductor device comprising:

• a first pair of gate electrodes arranged in a first layer and elongated in a row electrode;
• a second pair of gate electrodes arranged in the first layer, and elongated in the row direction;
• first self-aligned contacts arranged between the gate electrodes of said first pair of gate electrodes at predetermined intervals in the row direction;
• second self-aligned contacts arranged between the gate electrodes of said second pair of gate electrodes at predetermined intervals in the row direction;
• a first row wire arranged in a second layer and electrically connected to said first self-aligned contact;
• a second row wire arranged in the second layer, and electrically connected to said second self-aligned contact;
• means arranged in the second layer at a first end in the row direction for setting said first row wire and said second row wire to a first potential;
• a first conductor arranged in the second layer, and connected to said first pair of gate electrodes at a second end in the row direction;
• and
• a second conductor arranged in the second layer, and connected to said second pair of gate electrodes at the second end in the row direction,
• wherein said first conductor and said second conductor are set to a second potential different from the first potential.

A semiconductor device comprising:

• a first interdigital gate electrode arranged in a first layer and elongated in a row direction;
• a second interdigital gate electrode arranged in the first layer, and elongated in the row direction;
• a first self-aligned contact arranged between digits of said first gate electrode;
• a second self-aligned contact arranged between digits of said second gate electrode;
• a first row wire arranged in a second layer, and electrically connected to said first self-aligned contact;
• a second row electrode arranged in the second layer, and electrically connected to said second self-aligned contact;
• means arranged in the second layer at a first end in the row direction for setting said first row wire and said second row wire to a first potential;
• a first conductor arranged in the second layer at a second end in the row electrode, and electrically connected to said first row wire;
• and
• a second conductor arranged in the second layer at the second end, and electrically connected to said second row wire,
• wherein said first conductor and said second conductor are set to a second potential different from the first potential.

A semiconductor device comprising:

• a first pair of gate electrodes arranged in a first layer, and elongated in a row direction;
• a second pair of gate electrodes arranged in the first layer, and elongated in the row direction;
• a series of first bit contacts arranged between said first pair of gate electrodes at predetermined intervals in the row direction;
• a series of second bit contacts arranged between said second part of gate electrodes at predetermined intervals in the row direction;
• a series of first active areas formed in the first layer, and having, on a surface, a diffusion layer connected to two adjacent bit contacts of said series of first bit contacts;
• a series of second active areas formed in the first layer, and having, on a surface, a diffusion layer connected to two adjacent bit contacts of said series of second bit contacts;
• a series of first wires for electrically connecting two adjacent bit contacts of said series of first bit contacts;
• a series of second wires for electrically connecting between two adjacent bit contacts of said series of second bit contacts;
• a first conductor electrically connected to a bit contact positioned at a first end in the row direction of said series of first bit contacts;
• a second conductor electrically connected to a bit contact positioned at a first end in the row direction of said series of second bit contacts;
• a third conductor electrically connected to said second pair of gate electrodes at the second ends of said first pair of gate electrodes;
• a fourth conductor electrically connected to said second pair of gate electrodes at the second ends of said second pair of gate electrodes in the row direction;
• and
• means arranged in the second layer for setting said series of first wires, said series of second wires, said first conductor, and said second conductor to a first potential,
• wherein said third conductor and said fourth conductor are set to a second potential different from the first potential.

A semiconductor device comprising a basic wiring pattern including:

• a first inverted C-shaped wire having a pair of parallel interdigital conductors;
• and
• a second inverted C-shaped wire having a pair of parallel interdigital conductors and arranged interdigitally with respect to said first wire,
• wherein said first wire and said second wire are set to electrically different potentials such that a short can be detected between said wires.

A semiconductor device comprising a basic wiring pattern including:

• a first inverted C-shaped wire having parallel interdigital conductors;
• and
• a second linear wire arranged between said parallel interdigital conductors,
• wherein said first wire and said second wire are set to electrically different potentials, such that a short can be detected between said wires.

A semiconductor device comprising a basic wiring pattern including:

• a first interdigital wire having a plurality of parallel interdigital conductors;
• and
• a second wire having a plurality of parallel interdigital conductor, and interdigitally arranged with respect to said first wire,
• wherein said first wire and said second wire are set to electrically different potentials, such that a short can be detected between said wires.

A semiconductor device comprising a basic wiring pattern including:

• a first zig-zag wire having a plurality of parallel conductors;
• and
• a second interdigital wire interdigitally arranged with respect to said first wire, said second wire having interdigital conductors positioned between opposing conductors of said first wire,
• wherein said first wire and said second wire are set to electrically different potentials, such that a short between said wires and an opened wire can be detected.

A semiconductor device comprising a basic wiring pattern including:

• a first interdigital wire having a plurality of parallel interdigital conductors;
• a second zig-zag wire having a plurality of parallel conductors, wherein at least a pair of said conductors are positioned between opposing interdigital conductors of said first wire;
• and
• a third interdigital wire having a plurality of parallel interdigital conductors extending in a direction opposite to the interdigital conductors of said first wire, and positioned between the opposing conductors of said second wire,
• wherein said second wire is set to a predetermined potential, and said first wire and said third wire are set to a potential different from the predetermined potential, such that a short between said wires, and an opened wire can be detected.

A semiconductor device having a first layer formed on a first side of an insulating layer, and a second layer formed on a second side opposite to the first side, said semiconductor device comprising:

• a group of TEG's having two or more TEG's, each including:
• a first row wire having a plurality of wires formed in said first layer and arranged at predetermined intervals in a row direction;
• a second row wire having a plurality of wires formed in said second layer so as to overlap said first row wire and include adjacent ends of said plurality of wires;
• and
• conductors such as vias and a contact for electrically connecting the wires in said first row wire to the wires in said second row wire,
• wherein said conductors are different in diameter or interval among different TEG's.