US 2009/0152590 A1 · METHOD AND STRUCTURE FOR SEMICONDUCTOR DEVICES WITH SILICON-GERMANIUM DEPOSITS

Method and structure for semiconductor devices with silicon-germanium deposits

AssigneesInternational Business Machines Corporation, Advanced Micro Devices, Inc. (Amd)

InventorsThomas N. Adam, Linda Black, Huajie Chen, Dureseti Chidambarrao, Robert E. Davis, Judson R. Holt, Randolph F. Knarr, Christian Lavoie, Robert J. Purtell, Dominic J. Schepis

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Abstract

A method of forming a semiconductor device including forming a second deposit of silicon-germanium on a first deposit of silicon-germanium, the first deposit formed in a conduction terminal region of a substrate of the semiconductor device and having a first percentage of germanium, and the second deposit having a second percentage of germanium that is less than the first percentage and supports forming a silicide deposit on the second deposit. A structure is also provided.

Claims20

Dependent claims

A method of forming a semiconductor device, the method comprising:

forming a second deposit of silicon-germanium on a first deposit of silicon-germanium, the first deposit formed in a conduction terminal region of a substrate of the semiconductor device and having a first percentage of germanium;
and
the second deposit having a second percentage of germanium that is less than the first percentage and supports forming a silicide deposit on the second deposit.

Dependencies are inferred from the claim text.

Facts

Application

11/955,488Filed 13 Dec 2007

Published

18 Jun 2009

Term ends

Not estimatedThe source records don’t support an estimate.

Classification6 codes

H10D 30/797
Arrangements for exerting mechanical stress on the crystal lattice of the channel regions: being in source or drain regions, e.g. SiGe source or drain
H10D 62/021
Manufacture or treatment: forming source or drain recesses by etching e.g. recessing by etching and then refilling
H10D 62/822
Heterojunctions: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
H10D 30/0212
Of FETs having insulated gates [IGFET]: using self-aligned silicidation