Deep guard regions for reducing latch-up in electronics devices

An integrated circuit, comprising:

• a semiconductor layer of a first conductivity;
• a well disposed in the layer and of a second conductivity;
• a first source/drain region formed in the well and of the first conductivity;
• a second source/drain region formed in the layer outside of the well and of the second conductivity;
• and
• a guard region disposed in the layer between the well and the second source/drain region and of the second conductivity.

A system, comprising:

• a first integrated circuit, comprising
• a semiconductor layer of a first conductivity,
• a well disposed in the layer and of a second conductivity,
• a first source/drain region formed in the well and of the first conductivity,
• a second source/drain region formed in the layer outside of the well and of the second conductivity, and
• a guard region disposed in the layer between the well and the second source/drain region and of the second conductivity;
• and
• a second integrated circuit coupled to the first integrated circuit.

A system, comprising:

• a first integrated circuit, comprising
• a semiconductor layer of a first conductivity,
• a silicon-controlled rectifier disposed in the layer and having an anode and a cathodes and
• a guard region disposed in the layer between the anode and the cathode and of a second conductivity;
• a second integrated circuit coupled to the first integrated circuit.

A method, comprising:

• forming in a semiconductor layer of a first conductivity first and second regions of a second conductivity;
• forming in the first region a third region of the first conductivity;
• and
• forming in the layer between the first and second regions a guard region of the second conductivity.