Memory device
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorHajime Tokunaga
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Abstract
A memory device is provided, which includes a memory element including a first electrode, a second electrode, and a silicon layer disposed between the first electrode and the second electrode. The memory element is capable of being in a first state, a second state, and a third state. A first data is written to the memory element being in the first state so that a potential of the first electrode is higher than a potential of the second electrode, whereby the memory element being in the second state is obtained. A second data is written to the memory element being in the first state so that a potential of the second electrode is higher than a potential of the first electrode, whereby the memory element being in the third state is obtained.
Claims20
A memory device comprising:
- a memory element including a first electrode, a second electrode, and a silicon layer disposed between the first electrode and the second electrode,
- wherein:
- the memory element is capable of being in a first state, a second state, and a third state,
- a first data is written to the memory element being in the first state so that a potential of the first electrode is higher than a potential of the second electrode, whereby the memory element being in the second state is obtained,
- a second data is written to the memory element being in the first state so that a potential of the second electrode is higher than a potential of the first electrode, whereby the memory element being in the third state is obtained, and
- R1>R2>R3 is satisfied when a resistance of the memory element being in the first state is R1, a resistance of the memory element being in the second state is R2, and a resistance of the memory element being in the third state is R3.
A memory device comprising:
- a memory element including a first electrode, a second electrode, and a silicon layer and an insulating layer which are disposed between the first electrode and the second electrode,
- wherein:
- the memory element is capable of being in a first state, a second state, and a third state,
- a first data is written to the memory element being in the first state so that a potential of the first electrode is higher than a potential of the second electrode, whereby the memory element being in the second state is obtained,
- a second data is written to the memory element being in the first state so that a potential of the second electrode is higher than a potential of the first electrode, whereby the memory element being in the third state is obtained, and
- R1>R2>R3 is satisfied when a resistance of the memory element being in the first state is R1, a resistance of the memory element being in the second state is R2, and a resistance of the memory element being in the third state is R3.
A memory device comprising:
- a memory element including a first electrode, a second electrode, and a silicon layer and an insulating layer which are disposed between the first electrode and the second electrode,
- wherein:
- the memory element is capable of being in a first state, a second state, and a third state,
- a first data is written to the memory element being in the first state so that a potential of the first electrode is higher than a potential of the second electrode, whereby the memory element being in the second state is obtained,
- a second data is written to the memory element being in the first state so that a potential of the second electrode is higher than a potential of the first electrode, whereby the memory element being in the third state is obtained, and
- R1>R2>R3 is satisfied when a resistance of the memory element being in the first state is R1, a resistance of the memory element being in the second state is R2, and a resistance of the memory element being in the third state is R3,
- the memory element being in the second state corresponds to the memory element in which one of “0” and “1” is written, and
- the memory element being in the third state corresponds to the memory element in which the other of “0” and “1” is written.
Dependencies are inferred from the claim text.