Back to results
US 2009/0152544 A1Published application
Disguising test pads in a semiconductor package
AssigneeSanDisk Corporation
InventorArie Frenklakh
Life of this patent
Estimating the term…
Abstract
A method of forming a semiconductor package is disclosed including disguising the test pads. Test pads are defined in the conductive pattern of the semiconductor package for allowing electrical test of the completed package. The test pads are formed in shapes such as letters or objects so that they are less recognizable as test pads.
Claims70
A method of fabricating a semiconductor package, the method comprising the steps of:
- (a) forming test pads on a surface of the semiconductor package, said step (a) of forming the test pads comprising the step of disguising a purpose of the test pads by forming the test pads into a shape that reduces a likelihood that the test pads are recognizable as test pads;
- and
- (b) testing the functioning of the semiconductor package via the test pads formed in said step (a).
A method of fabricating a semiconductor package, the method comprising the steps of:
- (a) forming test pads on a surface of the semiconductor package, said step (a) of forming the test pads comprising the step of disguising a purpose of the test pads by forming the test pads into the shape of one or more letters and/or objects;
- and
- (b) testing the functioning of the semiconductor package via the test pads formed in said step (a).
A method of fabricating a semiconductor package, the method comprising the steps of:
- (a) forming a first electrically conductive pad on a substrate of the semiconductor package in the shape of at least a portion of a first letter;
- (b) forming at least a second electrically conductive pad on a substrate, adjacent the first electrically conductive pad, in the shape of at least a portion of a second letter;
- and
- (c) testing the functioning of the semiconductor package via the first and at least second electrically conductive pads formed in said steps (a) and (b).
1 more element
A semiconductor package, comprising:
- a substrate having a conductive pattern, the conductive pattern including test pads for allowing electrical test of the semiconductor package, the test pads shaped into a shape that reduces a likelihood that the test pads are recognizable as test pads;
- one or more semiconductor die coupled to the substrate;
- and
- molding compound encapsulating the one or more semiconductor die and at least a portion of the substrate.
1 more element
A semiconductor package, comprising:
- a substrate having a conductive pattern, the conductive pattern including test pads for allowing electrical test of the semiconductor package, the test pads shaped into letters and/or an object for disguising the test pads;
- one or more semiconductor die coupled to the substrate;
- and
- molding compound encapsulating the one or more semiconductor die and at least a portion of the substrate.
1 more element
A method of covering test pads of a semiconductor package, the method comprising the steps of:
- (a) covering the test pads with a cover;
- and
- (b) disguising the cover by including a marking on the cover to reduce the likelihood that the cover is recognizable as covering the test pads.
A method of fabricating a semiconductor package including test pads, the method comprising the steps of:
- (a) defining a conductive pattern on a substrate, the conductive pattern including test pads for allowing electrical test of the semiconductor package;
- (b) mounting one or more semiconductor die on the substrate;
- (c) electrically coupling the semiconductor die to the substrate;
- (d) encapsulating the semiconductor die and at least part of the substrate in a molding compound to form the semiconductor package;
- (e) electrically testing the semiconductor package via the test pads;
- (f) covering the test pads with a cover;
- and
- (g) disguising the cover by including a marking on the cover to reduce the likelihood that the cover is recognizable as covering the test pads.
5 more elements
A method of fabricating a semiconductor package including test pads, the method comprising the steps of:
- (a) defining a conductive pattern on a substrate, the step (a) including the step of defining test pads on the substrate in a non-standard location on the substrate and/or in a non-standard configuration on the substrate;
- (b) coupling the one or more semiconductor die on the substrate;
- (c) covering the test pads with a cover;
- and
- (d) disguising the cover by including a marking on the cover, the marking on the cover, and the non-standard location and/or configuration of the test pads, reducing the likelihood that the cover is recognizable as covering the test pads.
2 more elements
A semiconductor package, comprising:
- a substrate having a conductive pattern, the conductive pattern including test pads for allowing electrical test of the semiconductor package;
- one or more semiconductor die coupled to the substrate;
- molding compound encapsulating the one or more semiconductor die and at least a portion of the substrate;
- a cover for covering the test pads;
- and
- a marking on the cover for disguising the cover by reducing the likelihood that the cover is recognizable as covering the test pads.
3 more elements
A semiconductor package, comprising:
- a substrate having a conductive pattern;
- one or more semiconductor die coupled to the substrate;
- molding compound encapsulating the one or more semiconductor die and at least a portion of the substrate;
- a cover for covering the test pads;
- and
- a marking on the cover for disguising the cover by reducing the likelihood that the cover is recognizable as covering the test pads;
- wherein the conductive pattern includes test pads for allowing electrical test of the semiconductor package, the test pads formed in a non-standard location and/or a non-standard configuration, for further disguising the cover by reducing the likelihood that the cover is recognizable as covering the test pads.
4 more elements
Dependencies are inferred from the claim text.