Memory Cells, And Methods Of Forming Memory Cells

A method of forming a memory cell, comprising:

• forming a dummy gate over a semiconductor substrate;
• using the dummy gate as a mask while implanting dopant into the semiconductor substrate to form source/drain regions;
• forming an electrically insulative material laterally along the dummy gate;
• removing the dummy gate to leave an opening extending through the electrically insulative material;
• annealing the dopant within the source/drain regions;
• and
• after annealing the dopant, forming nanosize charge trapping units within the opening, forming dielectric material within the opening and over the charge trapping units, and forming control gate material within the opening and over the dielectric material.

A method of forming a memory cell, comprising:

• forming a first sacrificial structure over a semiconductor substrate;
• using the first sacrificial structure as a first mask while implanting first dopant into the semiconductor substrate to form lightly doped portions of a pair of source/drain regions, the individual source drain regions of said pair being spaced from one another by a channel region location beneath the first mask;
• forming second sacrificial structures along opposing sidewalls of the first sacrificial structure;
• using the combined first and second sacrificial structures as a second mask while implanting second dopant to form heavily doped portions of the source/drain regions;
• forming an electrically insulative material laterally along the second mask;
• removing the first sacrificial structure to form a first opening extending between the second sacrificial structures;
• implanting third dopant into the first opening to form a threshold voltage implant within the channel region location;
• removing the second sacrificial structures to laterally expand the first opening into a second opening that extends through the electrically insulative material;
• annealing the first, second and third dopants;
• and
• after annealing the first, second and third dopants, forming nanosize charge trapping units within the second opening, forming dielectric material within the second opening and over the charge trapping units, and forming control gate material within the second opening and over the dielectric material.

A memory cell, comprising:

• a pair of source/drain regions extending into a semiconductor substrate, the source/drain regions being spaced from one another by a channel region;
• a plurality of nanosized islands of charge trapping material over the channel, adjacent islands being spaced from one another by gaps;
• dielectric material over and between the nanosized islands, the dielectric material forming a container shape having an upwardly opening trough therein;
• and
• control gate material within the trough.