Multiplexer circuit
AssigneeKorea Advanced Institute of Science and Technology
InventorsKyoung Hoon YANG, Tae Ho KIM
Life of this patent
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Abstract
Disclosed herein is a multiplexer circuit. The multiplexer circuit includes a first differential output unit, a second differential output unit, and a selection unit. The first differential output unit receives NRZ input signals (D1, and D1) and a clock signal (CLK), and generates differential RZ-mode outputs (R1 and R1). The second differential output unit receives NRZ input signals (D2 and D2) and an inverted clock signal ( CLK), and generates differential RZ-mode outputs (R2 and R2). The selection unit receives the RZ-mode output signals (R1, R1, R2, and R2) generated at the first differential output unit and the second differential output unit, and generates NRZ mode outputs in each half cycle of the clock signal (CLK).
Claims9
A multiplexer circuit, comprising:
- a first differential output unit for receiving NRZ input signals (D1 and D1) and a clock signal (CLK), and generating differential RZ-mode outputs (R1 and R1);
- a second differential output unit for receiving NRZ input signals (D2 and D2) and an inverted clock signal ( CLK), and generating differential RZ-mode outputs (R2 and R2);
- and
- a selection unit for receiving the RZ-mode output signals (R1, R1, R2, and R2) generated at the first differential output unit and the second differential output unit, and generating NRZ mode outputs in each half cycle of the clock signal (CLK).
Dependencies are inferred from the claim text.