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US 2009/0067431 A1Published application
High performance network adapter (hpna)
AssigneeLiquid Computing Corporation
InventorsKaiyuan HUANG, Kenneth E. Neudorf, Michael F. Kemp
Life of this patent
Estimating the term…
Abstract
A high performance network adapter is provided for forwarding traffic and providing adaptation between packetized memory fragment based processor links of multiple CPUs and multiple switch planes of a packet switching network. Low latency for short and long packets is provided by innovative packet reassembly, overlapping transmission, and reverse order transmission in the upstream direction, and cut through operation in the downstream direction.
Claims73
A network adapter, comprising:
- an array of downstream packet processors, each downstream packet processor being configured to process an incoming data packet received from a network, and
- an upstream packet processor, the upstream packet processor being configured to process an outgoing data packet to be transmitted over the network, the upstream packet processor including:
- a direct memory access (DMA) engine configured to read the outgoing data packet from a memory of a processor and to transfer the read outgoing data packet;
- a packet buffer, and
- a reassembly state machine (RSM) configured to receive the transferred outgoing data packet from the processor as a plurality of out-of-order fragments and to store the received plurality of out-of-order fragments in the packet buffer in a correct sequential order as a reassembled outgoing data packet.
2 more elements
A computer, comprising:
- a network;
- a plurality of compute modules, each compute module being coupled to the packet network and each including:
- a plurality of processors, and
- a network adapter, the network adapter being coupled to each of the plurality of processors, the network adapter including:
- an array of downstream packet processors, each downstream packet processor being configured to process an incoming data packet received from the network, and
- an upstream packet processor, the upstream packet processor being configured to process an outgoing data packet to be transmitted over the network, the upstream packet processor including:
- a direct memory access (DMA) engine configured to read the outgoing data packet from a memory of a processor and to transfer the read outgoing data packet;
- a packet buffer, and
- a reassembly state machine (RSM) configured to receive the transferred outgoing data packet from the processor as a plurality of out-of-order fragments and to store the received plurality of out-of-order fragments in the packet buffer in a correct sequential order as a reassembled outgoing data packet.
6 more elements
A method of sending a data packet over a network of a computer system, comprising the steps of:
- providing a network adapter;
- fragmenting the data packet into a plurality of fragments;
- beginning to send the plurality of fragments to the network adapter;
- after the network adapter has received some but not all of the plurality of fragments, transmitting the received fragments from the network adapter to the network;
- after the network adapter has begun transmitting the received fragments over the network but before all of the data packet is transmitted to the network, receiving any remaining fragments of the data packet into the network adapter, and
- transmitting the received remaining fragments from the network adapter to the network.
3 more elements
A computer, comprising:
- a packet switching network;
- a processor;
- a network adapter, the network processor being coupled to the processor and to the packet switching network, the network adapter being configured to receive constituent fragments of a data packet to be sent over the packet switching network from the processor and to transmit at least one received fragment to the packet switching network before having received all of the constituent fragments of the outgoing data packet from the processor.
A method for receiving and processing a plurality of data packets from a plurality of processors, each of the data packets including a plurality of fragments that are ordered according to a first order, the method comprising the steps of:
- providing a packet buffer;
- providing a reassembly state machine (RSM) coupled to the packet buffer;
- providing a direct memory access engine configured to read the data packets from at least one of the plurality of processors and to transfer the read data packets to the RSM;
- receiving, in the RSM, the transferred data packets as a plurality of fragments in a second order that is different from the first order, each received fragment including a data fragment and an associated fragment address, and
- storing the fragment data of each of the received plurality of fragments in the packet buffer at the fragment address associated with the received data fragment, such that the transferred data packets are reassembled and stored in the packet buffer in the first order.
2 more elements
A method of transmitting a data packet stored in a memory of a processor to a network, comprising the steps of:
- providing a network adapter, the network adapter including a reassembly state machine (RSM), a packet buffer, a Packet Output Queue (POQ) and a physical I/O block coupled to the POQ and to the network;
- fragmenting the stored data packet into a plurality of fragments, each including a plurality of words, and transmitting the plurality of fragments to the RSM;
- sending fragments from the RSM to the packet buffer and storing the sent fragments in the packet buffer;
- sending a first word of a first of the plurality of fragments and a last word of a last of the plurality of fragments from the RSM to the POQ and storing the first and last words in the POQ;
- accessing, by the POQ, the packet buffer and retrieving therefrom all but the first and last words of the data packet in reverse order, and
- sending a modified data packet that includes the first word, the last word and the words retrieved from the packet buffer to the physical I/O block for transmission to the network.
3 more elements
A method for transmitting a data packet stored in a memory of a processor to a network, comprising the steps of:
- providing a network adapter, the network adapter including a reassembly state machine (RSM), a packet buffer, a Packet Output Queue (POQ) and a physical I/O block coupled to the POQ and to the network;
- fragmenting the stored data packet into a plurality of fragments, each including a plurality of words, and transmitting the plurality of fragments to the RSM;
- sending fragments from the RSM to the packet buffer and storing the sent fragments in the packet buffer;
- sending a first word of a first of the plurality of fragments and a last word of a last of the plurality of fragments from the RSM to the POQ and storing the first and last words in the POQ;
- accessing, by the POQ, the packet buffer and retrieving therefrom all but the first and last words of the data packet, and
- sending the first word, the words retrieved from the packet buffer and the last word to the physical I/O block for transmission to the network.
3 more elements
A method for transmitting a data packet stored in a memory of a processor to a packet switching network that includes a plurality of switch planes, comprising the steps of:
- providing a network adapter, the network adapter including a reassembly state machine (RSM), a packet buffer, and a plurality of Packet Output Queue (POQ), one POQ being associated with each of the plurality of switch planes;
- fragmenting the stored data packet into a plurality of fragments, each including a plurality of words, and transmitting the plurality of fragments to the RSM;
- sending fragments from the RSM to the packet buffer and storing the sent fragments in the packet buffer;
- storing, by the RSM, a first word of a first of the plurality of fragments and a last word of a last of the plurality of fragments in each of the plurality of POQ;
- selecting one of the plurality of switch planes;
- accessing, by the POQ associated with the selected switch plane, the packet buffer and retrieving therefrom all but the first and last words of the data packet to reassemble the data packet, and
- transmitting the reassembled data packet to the selected switch plane.
4 more elements
Dependencies are inferred from the claim text.