Method and program for designing semiconductor integrated circuit

A design program recorded on a computer-readable medium that, when executed, causes a computer to perform a method of designing a semiconductor integrated circuit, the method comprising:

• generating a delay library for use in a statistical static timing analysis, wherein said delay library provides a delay function that expresses a delay value of a cell as a function of a model parameter of a transistor in said cell;
• generating a layout data indicating a layout of said semiconductor integrated circuit;
• and
• calculating a delay value of a target cell included in said semiconductor integrated circuit, based on said delay library and said layout data,
• wherein said calculating the delay value of the target cell comprises:
• referring to said layout data to extract a parameter that specifies a layout pattern around a target transistor included in said target cell;
• modulating a model parameter of said target transistor such that a characteristic of said target transistor corresponding to said extracted parameter is obtained in a circuit simulation;
• calculating, by using said delay function, a reference delay value that is a reference of a delay value of said target cell;
• and
• calculating, by using said delay function and the modulation amount of said model parameter in said modulating, a delay variation that is a variation of said delay value of said target cell from said reference delay value and depends on said modulation amount.

A delay calculation program recorded on a computer-readable medium that, when executed, causes a computer to perform a method of calculating a delay value of a cell in a semiconductor integrated circuit, the method comprising:

• reading a layout data indicating a layout of said semiconductor integrated circuit from a memory device;
• reading a delay library for use in a statistical static timing analysis from said memory device, wherein said delay library provides a delay function that expresses a delay value of a cell as a function of a model parameter of a transistor in said cell;
• and
• calculating a delay value of a target cell included in said semiconductor integrated circuit, based on said delay library and said layout data, wherein said calculating the delay value of the target cell comprises:
• referring to said layout data to extract a parameter that specifies a layout pattern around a target transistor included in said target cell;
• modulating a model parameter of said target transistor such that a characteristic of said target transistor corresponding to said extracted parameter is obtained in a circuit simulation;
• calculating, by using said delay function, a reference delay value that is a reference of a delay value of said target cell;
• and
• calculating, by using said delay function and the modulation amount of said model parameter in said modulating, a delay variation that is a variation of said delay value of said target cell from said reference delay value and depends on said modulation amount.