Method and program for designing semiconductor integrated circuit
AssigneeNEC Electronics Corporation
InventorKenta Yamada
Life of this patent
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Abstract
A method of designing a semiconductor integrated circuit includes: performing a circuit simulation of a cell with changing a parameter that specifies a layout pattern around the cell; and generating a delay function expressing a delay value of the cell as a function of the parameter, based on a result of the circuit simulation. The method further includes: generating a layout data indicating a layout of the semiconductor integrated circuit, based on a cell-based design technique. The method further includes: referring to the generated layout data to extract the parameter associated with a target cell included in the semiconductor integrated circuit; and calculating a delay value of the target cell by using the extracted parameter and the delay function.
Claims11
A method of designing a semiconductor integrated circuit comprising:
- performing a circuit simulation of a cell with changing a parameter that specifies a layout pattern around said cell;
- generating a delay function expressing a delay value of said cell as a function of said parameter, based on a result of said circuit simulation;
- generating a layout data indicating a layout of said semiconductor integrated circuit, based on a cell-based design technique;
- referring to said generated layout data to extract said parameter associated with a target cell included in said semiconductor integrated circuit;
- and
- calculating a delay value of said target cell by using said extracted parameter and said delay function.
A design program recorded on a computer-readable medium that, when executed, causes a computer to perform a method of designing a semiconductor integrated circuit, the method comprising:
- performing a circuit simulation of a cell with changing a parameter that specifies a layout pattern around said cell;
- generating a delay function expressing a delay value of said cell as a function of said parameter, based on a result of said circuit simulation;
- generating a layout data indicating a layout of said semiconductor integrated circuit, based on a cell-based design technique;
- referring to said generated layout data to extract said parameter associated with a target cell included in said semiconductor integrated circuit;
- and
- calculating a delay value of said target cell by using said extracted parameter and said delay function.
A delay calculation program recorded on a computer-readable medium that, when executed, causes a computer to perform a method of calculating a delay value of a cell based on a layout data of a semiconductor integrated circuit, the method comprising:
- reading a delay library from a memory device, wherein said delay library provides a delay function expressing a delay value of a cell as a function of a parameter that specifies a layout pattern around said cell;
- referring to said layout data to extract said parameter associated with a target cell included in said semiconductor integrated circuit;
- and
- calculating a delay value of said target cell by using said extracted parameter and said delay function.
Dependencies are inferred from the claim text.