Method of designing semiconductor integrated circuit and mask data generation program

A method of designing a semiconductor integrated circuit comprising:

• generating a layout data indicating a layout of said semiconductor integrated circuit;
• and
• generating a mask data of said semiconductor integrated circuit based on said layout data,
• wherein said generating the mask data comprises:
• referring to said layout data to extract a parameter that specifies a layout pattern around a target transistor included in said semiconductor integrated circuit, wherein said parameter includes at least a width of a device isolation structure around said target transistor;
• correcting a gate length and a gate width of said target transistor to offset a variation of a characteristic of said target transistor from a design value, said variation depending on said extracted parameter;
• and
• generating said mask data from said layout data in which said gate length and said gate width are corrected.