Turbo coding having combined turbo de-padding and rate matching de-padding

A turbo encoder performing combined turbo de-padding and rate matching de-padding, the turbo encoder comprising:

• a zero padding module that is operable selectively not to pad any zero-valued bits or to pad one or more zero-valued bits to an information bit stream thereby generating a zero padded information bit stream;
• a turbo encoding module that is operable encode the zero padded information bit stream thereby generating a plurality of systematic bits, a first plurality of parity bits, and a second plurality of parity bits;
• a dummy padding module that is operable selectively not to pad any dummy bits or to pad one or more dummy bits to each of the plurality of systematic bits, the first plurality of parity bits, and the second plurality of parity bits thereby generating a plurality of dummy padded systematic bits, a first plurality of dummy padded parity bits, and a second plurality of dummy padded parity bits;
• a sub-block interleaving module that is operable to:
• perform first interleaving to the plurality of dummy padded systematic bits thereby generating a plurality of sub-block interleaved dummy padded systematic bits;
• perform the first interleaving to the first plurality of dummy padded parity bits thereby generating first plurality of sub-block interleaved, dummy padded parity bits;
• and
• perform second interleaving to the second plurality of dummy padded parity bits thereby generating second plurality of sub-block interleaved, dummy padded parity bits;
• and
• one de-padding module that is operable to de-pad any zero padded bits and any dummy padded bits from each of the plurality of sub-block interleaved dummy padded systematic bits, the first plurality of sub-block interleaved, dummy padded parity bits, and the second plurality of sub-block interleaved, dummy padded parity bits thereby generating an output information bit stream;
• and wherein:
• the output information bit stream undergoes modulation to generate a turbo coded signal that comports with a communication channel;
• the turbo coded signal is launched into the communication channel;
• and
• of the plurality of sub-block interleaved dummy padded systematic bits, the first plurality of sub-block interleaved, dummy padded parity bits, and the second plurality of sub-block interleaved, dummy padded parity bits, the one de-padding module is operable to de-pad zero padded bits from only the plurality of sub-block interleaved dummy padded systematic bits and the first plurality of sub-block interleaved, dummy padded parity bits.

A method for performing combined turbo de-padding and rate matching de-padding, the method comprising:

• selectively not padding any zero-valued bits or padding one or more zero-valued bits to an information bit stream thereby generating a zero padded information bit stream;
• turbo encoding the zero padded information bit stream thereby generating a plurality of systematic bits, a first plurality of parity bits, and a second plurality of parity bits;
• selectively not padding any dummy bits or padding one or more dummy bits to the plurality of systematic bits, the first plurality of parity bits, and the second plurality of parity bits thereby generating at least one of a plurality of dummy padded systematic bits, a first plurality of dummy padded parity bits, and a second plurality of dummy padded parity bits;
• performing sub-block interleaving on at least one of the plurality of dummy padded systematic bits, the first plurality of dummy padded parity bits, and the second plurality of dummy padded parity bits thereby generating at least one of a plurality of sub-block interleaved dummy padded systematic bits, a first plurality of sub-block interleaved, dummy padded parity bits, and a second plurality of sub-block interleaved, dummy padded parity bits;
• and
• de-padding any zero padded bits and any dummy padded bits from each of the plurality of sub-block interleaved dummy padded systematic bits, the first plurality of sub-block interleaved, dummy padded parity bits, and the second plurality of sub-block interleaved, dummy padded parity bits thereby generating an output information bit stream.