Refresh of non-volatile memory cells based on fatigue conditions
AssigneeMicron Technology, Inc.
InventorsFrankie F. Roohparvar, Vishal Sarin, Jung-Sheng Hoei
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Abstract
In one or more of the disclosed embodiments, memory cells in a memory device are refreshed upon an indication of a fatigue condition. In one such embodiment, controller monitors behavior parameters of the cells and determines if any of the parameters are outside of a normal range set for each one, thus indicating a fatigue condition. If any cell indicates a fatigue condition, the data from the block of cells indicating the fatigue is moved to another block. In one embodiment, an error detection and correction process is performed on the data prior to being written into another memory block.
Claims23
A method for refreshing non-volatile memory cells in a memory array, the method comprising:
- monitoring behavior parameters of non-volatile memory cells for indications of degradation;
- and
- moving data stored in the non-volatile memory cells, exhibiting the indications of degradation of the behavior parameters, to other memory cells in the memory array.
A method for refreshing fatigued, non-volatile memory cells in a memory array, the method comprising:
- monitoring behavior parameters of non-volatile memory cells in a first memory block;
- if any of the behavior parameters are outside of an operational range for each parameter, reading data out of each memory cell in the first memory block;
- performing an error correction operation on the data from each memory cell to create error corrected data;
- and
- writing the error corrected data into non-volatile memory cells of a second memory block.
A memory device comprising:
- a memory array comprising a plurality of memory cells;
- and
- a memory controller coupled to the memory array for controlling operation of the memory array, the memory controller adapted to monitor for fatigue conditions of the plurality of memory cells and refresh the memory cells by moving data from a first memory cell indicating a fatigue condition to a second memory cell.
A solid state bulk storage system comprising:
- a memory device comprising a plurality of memory cells adapted to store analog voltages that are representative of digital bit patterns;
- a controller coupled to the memory device for controlling operation of the memory device, the controller adapted to monitor fatigue conditions of the memory cells and to transfer data from a first memory block, comprising a memory cell indicating at least one fatigue condition, to a second memory block;
- and
- a read/write channel for coupling the controller to the memory device and providing analog-to-digital conversion of the analog voltages to the digital bit patterns and digital-to-analog conversions of the digital bit patterns to the analog voltages.
Dependencies are inferred from the claim text.