System and method for predicting iwarx and stwcx instructions in test pattern generation and simulation for processor design verification/validation in interrupt mode

A peripheral device comprising:

• one or more processors;
• a memory accessible by at least one of the processors;
• a nonvolatile storage area accessible by at least one of the processors;
• a set of instructions stored in the memory and executed by at least one of the processors in order to perform actions of:
• selecting a lwarx instruction;
• pseudo-randomly selecting an address for the lwarx instruction;
• building the lwarx instruction using the pseudo-random address into a test pattern;
• building a store instruction after the lwarx instruction using the pseudo-random address, wherein the store instruction is adapted to store the pseudo-random address in a predetermined memory location;
• and
• building an interrupt service routine, wherein the interrupt service routine further comprises:
• servicing an interrupt associated with the interrupt request;
• after servicing the interrupt, checking the predetermined memory location;
• determining that the pseudo-random address is located in the predetermined memory location;
• and
• in response to determining that the pseudo-random address is located in the predetermined memory location, executing a subsequent lwarx instruction using the pseudo-random address.

A computer program product stored in a computer readable medium, comprising functional descriptive material that, when executed by an information handling system, causes the information handling system to perform actions that include:

• selecting a lwarx instruction;
• pseudo-randomly selecting an address for the lwarx instruction;
• building the lwarx instruction using the pseudo-random address into a test pattern;
• building a store instruction after the lwarx instruction using the pseudo-random address, wherein the store instruction is adapted to store the pseudo-random address in a predetermined memory location;
• and
• building an interrupt service routine, wherein the interrupt service routine further comprises:
• servicing an interrupt associated with the interrupt request;
• after servicing the interrupt, checking the predetermined memory location;
• determining that the pseudo-random address is located in the predetermined memory location;
• and
• in response to determining that the pseudo-random address is located in the predetermined memory location, executing a subsequent lwarx instruction using the pseudo-random address.