US 2009/0024892 A1Published application

System and Method of Testing using Test Pattern Re-Execution in Varying Timing Scenarios for Processor Design Verification and Validation

AssigneeInternational Business Machines Corporation

InventorsVinod Bussa, Manoj Dusanapudi, Sunil Suresh Hatti, Shakti Kapoor, Rahul Sharad Moharil, Bhavani Shringari Nanjundiah

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Abstract

A system and method processor testing using test pattern re-execution is presented. A processor re-executes test patterns using different timing scenarios in order to reduce test pattern build time and increase system test coverage. The invention described herein varies initial states of a processor's memory (cache, TLB, SLB, etc.) that, in turn, varies the timing scenarios when re-executing test patterns. By re-executing the test patterns instead of rebuilding new test patterns, verification quality is improved since more time is available for execution, verification and validation. In addition, since the test patterns result in the same final state, the invention described herein also simplifies error checking.

Claims20

Dependent claims

A computer-implemented method comprising:

simultaneously executing a first test pattern on a first processor and a second test pattern on a second processor, resulting in a first test pattern execution round;
after the first test pattern execution round, computing a first hardware register error detection check value;
comparing the first hardware register error detection check value to a simulation register error detection check value;
after the comparing, simultaneously re-executing the first test pattern on the first processor and re-executing the second test pattern on the second processor, resulting in a second test pattern execution round;
after the second test pattern execution round, computing a second hardware register error detection check value;
comparing the second hardware register error detection check value to the simulation register error detection check value;
and
setting an error flag if the first hardware register error detection check value or the second hardware register error detection check value do not match the simulation register error detection check value based upon the comparison.

5 more elements

An information handling system comprising:

one or more processors;
a memory accessible by the processors;
one or more nonvolatile storage devices accessible by the processors;
and
a set of instructions stored in the memory, wherein one or more of the processors executes the set of instructions in order to perform actions of:
simultaneously executing a first test pattern on a first processor and a second test pattern on a second processor, resulting in a first test pattern execution round;
after the first test pattern execution round, computing a first hardware register error detection check value;
comparing the first hardware register error detection check value to a simulation register error detection check value;
after the comparing, simultaneously re-executing the first test pattern on the first processor and re-executing the second test pattern on the second processor, resulting in a second test pattern execution round;
after the second test pattern execution round, computing a second hardware register error detection check value;
comparing the second hardware register error detection check value to the simulation register error detection check value;
and
setting an error flag if the first hardware register error detection check value or the second hardware register error detection check value do not match the simulation register error detection check value based upon the comparison.

10 more elements

A computer program product stored on a computer operable media, the computer operable media containing instructions for execution by a computer, which, when executed by the computer, cause the computer to implement a method of processing test patterns, the method comprising:

simultaneously executing a first test pattern on a first processor and a second test pattern on a second processor, resulting in a first test pattern execution round;
after the first test pattern execution round, computing a first hardware register error detection check value;
comparing the first hardware register error detection check value to a simulation register error detection check value;
after the comparing, simultaneously re-executing the first test pattern on the first processor and re-executing the second test pattern on the second processor, resulting in a second test pattern execution round;
after the second test pattern execution round, computing a second hardware register error detection check value;
comparing the second hardware register error detection check value to the simulation register error detection check value;
and
setting an error flag if the first hardware register error detection check value or the second hardware register error detection check value do not match the simulation register error detection check value based upon the comparison.

5 more elements

Dependencies are inferred from the claim text.