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US 2009/0024883 A1Published application
Inter-asic data transport using link control block manager
AssigneeCray Inc.
InventorRoger A. Bethard
Life of this patent
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Abstract
An apparatus comprising a SerDes circuit and a link control block (LCB). The SerDes circuit is a first end of a SerDes circuit pair of a SerDes lane. A SerDes lane includes the SerDes circuit pair coupled by a communications medium. The LCB includes an error tracking circuit and a controller. The controller includes an error recovery module configured to retry a data communication when an error is detected and deactivate the SerDes lane when a rate of errors on the SerDes lane exceeds a threshold error rate value. Other devices, systems, and methods are disclosed.
Claims30
An apparatus comprising:
- a serializer/deserializer (SerDes) circuit, wherein the SerDes circuit is a first end of a SerDes circuit pair of a SerDes lane, wherein a SerDes lane includes the SerDes circuit pair coupled by a communications medium;
- and
- a link control block (LCB) communicatively coupled to the SerDes circuit, the LCB including:
- an error tracking circuit;
- and
- a controller, communicatively coupled to the error tracking circuit, including an error recovery module configured to:
- retry a data communication when an error is detected;
- and
- deactivate the SerDes lane when a rate of errors on the SerDes lane exceeds a threshold error rate value.
6 more elements
A system comprising:
- a communications medium;
- and
- a first integrated circuit (IC) and a second IC each including:
- a plurality of serializer/deserializer (SerDes) circuits;
- and
- a link control block (LCB) communicatively coupled to the SerDes circuits, the LCB including:
- an error tracking circuit;
- and
- a controller, communicatively coupled to the error tracking circuit,
- wherein the controller includes an error recovery module configured to:
- retry a data communication when an error is detected;
- and
- deactivate a SerDes lane when a rate of errors on the SerDes lane exceeds a threshold error rate value, and
- wherein the first IC includes a first end of a SerDes circuit pair and the second IC includes a second end of a SerDes circuit pair, wherein a SerDes circuit pair coupled by the communications medium forms a SerDes lane, and wherein a plurality of SerDes lanes form a SerDes channel between the first IC and the second IC.
11 more elements
A method comprising:
- communicating data between a first integrated circuit (IC) and a second IC using a plurality of SerDes lanes, wherein each SerDes lane includes at least one SerDes circuit pair, and wherein the plurality of SerDes lanes defines a SerDes channel between the first IC and the second IC;
- tracking an error rate during the communicating;
- retrying a data communication when an error is detected;
- and
- automatically removing a SerDes lane from the SerDes channel when a rate of errors on the SerDes lane exceeds a threshold error rate value.
2 more elements
Dependencies are inferred from the claim text.