Method for monitoring an internal control signal of a memory device and apparatus therefor

An apparatus for monitoring an internal control signal of a memory device, comprising:

• a pulse width adjustment unit for receiving an input signal and a clock signal, and changing a pulse width of the input signal according to an operating frequency of the memory device;
• a signal transferring unit for buffering a signal output from the pulse width adjustment unit;
• an output unit for receiving a signal output from the signal transferring unit and outputting a first signal for controlling an operation of a data bus;
• and
• an output buffer for receiving and transferring the first signal externally of the memory device.

A method for monitoring an internal control signal of a memory device, comprising the steps of:

• (a) generating a first signal having a first pulse width by a burst operation command;
• (b) receiving the first signal, and generating N−1 (where, N is a burst length) second signals having a second pulse width;
• (c) receiving the first signal and the second signals, and outputting a third signal by changing the first pulse width of the first signal and the second pulse width of the second signals in accordance with a CAS (Column Address Strobe) latency of the memory device;
• (d) outputting the third signal to an external pin of the memory device and monitoring the third signal;
• and
• (e) adjusting a pulse width of a signal that controls an operation of a data bus connecting a bit-line sense amplifier and a data sense amplifier using the third signal.