US 2009/0024877 A1 · System and Method for Creating Different Start Cache and Bus States Using Multiple Test Patterns for Processor Design Verification and Validation

Abstract

A system and method for creating different start cache and bus states using multiple test patterns for processor design verification and validation is presented. A test pattern generator/tester re-uses test patterns in different configurations that alter cache states and translation lookaside buffer (TLB) states, which produces different timing scenarios on a broadband bus. The test pattern generator/tester creates multiple test patterns for a multi-processor system and executes the test patterns repeatedly in different configurations without rebuilding the test patterns. This enables a system to dedicate more time executing the test patterns instead of building the test patterns. By repeatedly executing the same test patterns in a different configuration, the invention described herein produces different start cache states, different TLB states, along with other processor units, each time the test patterns execute that, in turn, changes the bus timing.

Claims20

Dependent claims

A computer-implemented method comprising:

performing a first execution round, wherein the first execution round includes executing a first test pattern on a first processor and executing a second test pattern on a second processor, resulting in a first set of bus contentions;
performing a second execution round, wherein the second execution round includes executing the second test pattern on the first processor and executing the first test pattern on the second processor, resulting in a second set of bus contentions;
and
testing a bus coupled to the first processor and the second processor based upon the first set of bus contentions and the second set of bus contentions, wherein the first set of bus contentions are different than the second set of bus contentions;
and
determining, based upon the testing, whether a bus arbitrator resolved the first set of bus contentions and the second set of bus contentions;
and
setting an error flag in response to determining that the bus arbitrator did not resolve the first set of bus contentions and the second set of bus contentions.

5 more elements

An information handling system comprising:

one or more processors;
a memory accessible by the processors;
one or more nonvolatile storage devices accessible by the processors;
and
a set of instructions stored in the memory, wherein one or more of the processors executes the set of instructions in order to perform actions of:
performing a first execution round, wherein the first execution round includes executing a first test pattern on a first processor and executing a second test pattern on a second processor, resulting in a first set of bus contentions;
performing a second execution round, wherein the second execution round includes executing the second test pattern on the first processor and executing the first test pattern on the second processor, resulting in a second set of bus contentions;
and
testing a bus coupled to the first processor and the second processor based upon the first set of bus contentions and the second set of bus contentions, wherein the first set of bus contentions are different than the second set of bus contentions;
and
determining, based upon the testing, whether a bus arbitrator resolved the first set of bus contentions and the second set of bus contentions;
and
setting an error flag in response to determining that the bus arbitrator did not resolve the first set of bus contentions and the second set of bus contentions.

10 more elements

A computer program product stored on a computer operable media, the computer operable media containing instructions for execution by a computer, which, when executed by the computer, cause the computer to implement a method of processing test patterns, the method comprising:

performing a first execution round, wherein the first execution round includes executing a first test pattern on a first processor and executing a second test pattern on a second processor, resulting in a first set of bus contentions;
performing a second execution round, wherein the second execution round includes executing the second test pattern on the first processor and executing the first test pattern on the second processor, resulting in a second set of bus contentions;
and
testing a bus coupled to the first processor and the second processor based upon the first set of bus contentions and the second set of bus contentions, wherein the first set of bus contentions are different than the second set of bus contentions;
and
determining, based upon the testing, whether a bus arbitrator resolved the first set of bus contentions and the second set of bus contentions;
and
setting an error flag in response to determining that the bus arbitrator did not resolve the first set of bus contentions and the second set of bus contentions.

5 more elements

Dependencies are inferred from the claim text.

System and Method for Creating Different Start Cache and Bus States Using Multiple Test Patterns for Processor Design Verification and Validation

Life of this patent

System and Method for Creating Different Start Cache and Bus States Using Multiple Test Patterns for Processor Design Verification and Validation

Life of this patent

Abstract

Claims20