System and Method for Verification of Cache Snoop Logic and Coherency Between Instruction & Data Caches for Processor Design Verification and Validation

An information handling system comprising:

• one or more processors;
• a memory accessible by the processors;
• one or more nonvolatile storage devices accessible by the processors;
• and
• a set of instructions stored in the memory, wherein one or more of the processors executes the set of instructions in order to perform actions of:
• executing a first instruction at a first address that results in loading a first cache line into an instruction cache;
• after the execution of the first instruction, executing a second instruction at a second address, which branches to a third address;
• in response to branching to the third address, executing a third instruction at the third address that results in loading the first cache line into a data cache;
• in response to executing the third instruction, modifying the first cache line in the data cache;
• in response to modifying the first cache line in the data cache, determining whether the first cache line in the instruction cache is updated;
• and
• setting an error flag in response to determining that the first cache line in the instruction cache was not updated.

A computer program product stored on a computer operable media, the computer operable media containing instructions for execution by a computer, which, when executed by the computer, cause the computer to implement a method of processing test patterns, the method comprising:

• executing a first instruction at a first address that results in loading a first cache line into an instruction cache;
• after the execution of the first instruction, executing a second instruction at a second address, which branches to a third address;
• in response to branching to the third address, executing a third instruction at the third address that results in loading the first cache line into a data cache;
• in response to executing the third instruction, modifying the first cache line in the data cache;
• in response to modifying the first cache line in the data cache, determining whether the first cache line in the instruction cache is updated;
• and
• setting an error flag in response to determining that the first cache line in the instruction cache was not updated.