US 2009/0024866 A1 · DIGITAL VLSI CIRCUIT AND IMAGE PROCESSING DEVICE INTO WHICH THE SAME IS ASSEMBLED

Abstract

A digital VLSI circuit is provided with functions in which the number of switching operations to supply electric power to each arithmetic operation unit is reduced in a restricted period of time while electric power supply is controlled for each arithmetic operation unit, so that low power consumption can be achieved in real pipe-line arithmetic operation. The VLSI circuit that performs each stage of the pipe-line arithmetic operation is comprised of a plurality of arithmetic operation units for carrying out arithmetic operations in synchronization with a clock signal, a detecting means for detecting completion of the stage in the arithmetic operation assigned to the arithmetic operation unit, and a clock signal supply control means for controlling supply/stop operation of the clock signal to each arithmetic operation unit, wherein the clock signal supply control means stops supplying the clock signal to a certain arithmetic operation unit when the detecting means detects the completion of the arithmetic operation assigned to the same, and restarts supplying the clock signal to all the arithmetic operation units for a next pipe-line arithmetic operation when the detecting means detects the completion of the arithmetic operations assigned to them.

Claims20

Dependent claims

Digital VLSI circuit characterized by comprising:

a plurality of arithmetic operation units executing arithmetic processing synchronized with clock working on each stage of pipeline arithmetic processing;
Detection means detecting end of arithmetic processing of stage in charge in the arithmetic operation unit;
and
clock signal supply control means controlling supply/stop of clock by each arithmetic operation unit;
wherein the clock signal supply control means stop clock signal supply for the arithmetic operation unit in which end of arithmetic processing is detected by the detection means;
and wherein clock signal supply restarts for all the arithmetic operation units for the next pipeline arithmetic processing when end of arithmetic processing is detected in all the arithmetic operation units by the detection means.

3 more elements

Digital VLSI circuit characterized by constitution comprising:

a plurality of arithmetic operation units executing arithmetic processing synchronized with clock and working on each stage of pipeline arithmetic processing;
detection means detecting end of arithmetic processing of stage in charge in the arithmetic operation unit;
Clock signal supply control means controlling ON/OFF of clock by the arithmetic operation units;
wherein the clock signal supply control means by the detection means, in the case that the next arithmetic operation unit ends of arithmetic processing is detected first between previous arithmetic operation unit and the next arithmetic operation unit adjacent each other in the pipeline arithmetic processing, stops clock signal supply for the next stage arithmetic operation unit, After stop of clock signal supply for the nest stage arithmetic operation unit, in the case that end of arithmetic processing of the previous stage arithmetic operation unit is detected, clock signal supply is restarted for the next stage pipeline operation for the next stage arithmetic operation unit.

1 more element

Digital VLSI circuit characterized by comprising:

a plurality of arithmetic operation unit executing arithmetic processing working of each stage of pipeline arithmetic processing;
detection means detecting end of arithmetic processing of stage in charge in the arithmetic operation unit;
and
power supply control means controlling power supply/stop by the arithmetic operation unit;
wherein power supply stops for the arithmetic operation units detected end of arithmetic processing by the detection means;
and
wherein power supply will be restarted for all the arithmetic operation units for the next pipeline arithmetic processing when end of arithmetic processing in all the arithmetic operation unit by the detection means.

4 more elements

Digital VLSI circuit characterized by comprising:

a plurality of arithmetic operation units executing arithmetic processing working on each stage of pipeline arithmetic processing;
and
detection methods detecting end of arithmetic processing of stage in charge in the arithmetic operation units and power supply control means controlling power supply/stop by the arithmetic operation unit;
wherein the power supply control means stop power supply for the next stage arithmetic operation unit, in the case that end of arithmetic processing of the next arithmetic operation unit is detected by the detection means first between the previous stage arithmetic operation unit and the next stage arithmetic operation unit adjacent mutually in the pipeline arithmetic processing;
and
wherein after stopping of power supply for the next stage arithmetic operation unit, in the case of detection of the end of arithmetic processing of the previous stage arithmetic operation unit, for the next pipeline arithmetic processing power supply restarts for the next stage arithmetic operation unit.

3 more elements

Dependencies are inferred from the claim text.

Digital vlsi circuit and image processing device into which the same is assembled

Life of this patent

Digital vlsi circuit and image processing device into which the same is assembled

Life of this patent

Abstract

Claims20