Mechanism for suppressing instruction replay in a processor

A method comprising:

• scheduling and issuing instruction operations for execution by an execution unit, and causing to be replayed, instruction operations that are determined to be incorrectly executed;
• predicting whether a given instruction operation will replay and providing an indication that the given instruction operation will replay;
• flagging the given instruction operation in response to detecting the indication during instruction decoding;
• inhibiting issue of the flagged instruction operation until a status associated with the flagged instruction is good.

A system comprising:

• a memory;
• a processor coupled to the memory, wherein the processor comprises:
• one or more execution units configured to execute instruction operations;
• a scheduler coupled to the one or more execution units and configured to issue the instruction operations for execution by the one or more execution units, and to cause instruction operations that are determined to be incorrectly executed to be replayed;
• a prediction unit configured to predict whether a given instruction operation will replay and to provide an indication that the given instruction operation will replay;
• a decode unit coupled to the scheduler and configured to decode instructions, wherein in response to detecting the indication, the decode unit is further configured to flag the given instruction operation;
• wherein the scheduler is further configured to inhibit issue of the flagged instruction operation until a status associated with the flagged instruction is good.