Technique for preserving cached information during a low power mode
AssigneeIntel Corporation
InventorsSanjeev Jahagirdar, Varghese George, Jose Allarey
Life of this patent
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Abstract
A technique to retain cached information during a low power mode, according to at least one embodiment. In one embodiment, information stored in a processor's local cache is saved to a shared cache before the processor is placed into a low power mode, such that other processors may access information from the shared cache instead of causing the low power mode processor to return from the low power mode to service an access to its local cache.
Claims30
An apparatus comprising:
- a first processor core to be placed in a low power mode, in which at least modified information stored within the first processor core's local cache is to be stored in a shared cache;
- a second processor core to access the shared cache for information accessible within the local cache prior to the first processor core entering the low power mode, the second processor core to access the shared cache instead of the local cache in response to the first processor core being placed into the low power mode.
A system comprising:
- a first processor having at least two processor cores, wherein at least one of the processor cores is to enter a low power mode, in which information stored in the at least one processor core's local cache is no longer accessible;
- a second processor having at least one processor core to access information from a shared cache if the at least one processor core is in the low power mode, the shared cache to store versions of information stored in each of the at least two processor core's local caches;
- a system memory to store versions of information stored in the shared cache;
- a memory controller through which the second processor's at least one processor cores are to access the system memory.
A method comprising:
- placing a first processor core into a low power mode, wherein the low power mode includes storing at least modified information from the first processor core's level one (L1) cache to a level two (L2) cache;
- accessing the L2 cache instead of the L1 cache in response to the the first processor core entering the low power mode;
- generating an access to system memory if information requested by the second processor core is not stored in the L2 cache.
A machine-readable medium having stored thereon a set of instructions, which if executed by a machine causes the machine to perform a method comprising:
- causing a first processor to access a cache shared between at least a second and a third processor instead of a local cache corresponding to one of the second and third processors in response to determining that at least one of the second and third processors has entered a low power mode, wherein entering the low power mode causes the at least one of the second and third processors to store information from its respective local cache to the shared cache and to gate a clock to the at least one of the second and third processors and to reduce power to the at least one of the second and third processors to substantially zero.
Dependencies are inferred from the claim text.