High Performance Multilevel Cache Hierarchy
AssigneeTexas Instruments Incorporated
InventorsRobert Nychka, Janardan Prasad, Nilesh Acharya, Aditya Rawal, Ambar Nawaz
Life of this patent
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Abstract
A digital system is provided with a hierarchical memory system having at least a first and second level cache and a higher level memory. If a requested data item misses in both the first cache level and in the second cache level, a line of data containing the requested data is obtained from a higher level of the hierarchical memory system. The line of data is allocated to both the first cache level and to the second cache level simultaneously.
Claims18
A method of operating a hierarchical memory system, comprising:
- determining if requested data is available in a first cache level of the hierarchical memory system in response to receiving a request;
- determining if the requested data is available in a second cache level of the hierarchical memory system;
- obtaining a line of data containing the requested data from a higher level of the hierarchical memory system if the requested data is not available in either the first cache level or in the second cache level;
- and
- allocating the line of data to both the first cache level and to the second cache level simultaneously.
A digital system having a hierarchical memory system comprising:
- a level 0 cache;
- a level 1 cache connected to the level 0 cache;
- a level 2 memory connected to the level 1 cache;
- a fill buffer connected to receive a line of data from the level 2 memory and to allocate the line of data to the level 0 cache and to the level 1 cache simultaneously.
A digital system with a hierarchical memory system, comprising:
- means for determining if an address of a write request hits in a first cache level of the hierarchical memory system in response to receiving the write request;
- means for determining if the address of the write request hits in a second cache level of the hierarchical memory;
- means for obtaining a line of data from another level of the hierarchical memory system if the address of the write request does not hit in either the first cache level or in the second cache level;
- means for merging write data received with the write request into the line of data;
- and
- means for allocating the line of merged data to both the first cache level and to the second cache level simultaneously.
Dependencies are inferred from the claim text.