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US 2009/0024790 A1Published application
Memory circuit system and method
AssigneeGoogle Inc.
InventorsSuresh Natarajan Rajan, Keith R. Schakel, Michael John Smith, David T. Wang, Frederick Daniel Weber
Life of this patent
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Abstract
A memory circuit system and method are provided in the context of various embodiments. In one embodiment, an interface circuit remains in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for performing various functionality (e.g. power management, simulation/emulation, etc.).
Claims20
A sub-system, comprising:
- an interface circuit adapted for coupling with a plurality of memory circuits and a system, the interface circuit operable to interface the memory circuits and the system for emulating at least one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits;
- wherein the at least one aspect includes at least one of a signal, a capacity, a timing, and a logical interface.
A method, comprising:
- interfacing a plurality of memory circuits and a system;
- and
- emulating at least one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits;
- wherein the at least one aspect includes at least one of a signal, a capacity, a timing, and a logical interface.
1 more element
A system, comprising:
- a plurality of memory circuits;
- and
- an interface circuit in communication with the plurality of memory circuits and a system, the interface circuit operable to interface the memory circuits and the system for emulating at least one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits;
- wherein the at least one aspect includes at least one of a signal, a capacity, a timing, and a logical interface.
1 more element
Dependencies are inferred from the claim text.