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US 2009/0024781 A1Published application
Data Bus Interface With Interruptible Clock
AssigneeThomson Licensing
InventorFriedrich Heizmann
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AssigneeThomson Licensing
InventorFriedrich Heizmann
Estimating the term…
In a data bus with asynchronous data transmission via a clock and a data line, the transmitted data are ascertained by sampling with a multiple of the data rate of the data bus. Sampling is done in this case with a clock which is not synchronous with the asynchronous clock of the data bus. For avoiding interferences which develop due to the unnecessary operation of the interface circuit with a high frequency clock when no data are currently transmitted, a control circuit is provided for detecting the beginning and the end of a data transmission. Only at the beginning of a data transmission, the interface circuit will be supplied with the required clock. After the end of the data transmission, the clock for the interface circuit will be switched off again. The control circuit is preferably designed as a state machine which reacts, without the need for clock signals, to the states on the data and clock line of the data bus.
Data bus interface with a clock and a data line, in which the beginning and the end of a data transmission, respectively, is indicated by unique state combinations of the clock and data line, wherein an interface circuit is provided which, in the receiving mode, ascertains the states of the clock and the data line by sampling with a multiple of the data rate and outputs the transmitted data, characterized in that a control circuit is provided for detecting the beginning and the end of the data transmission, wherein the control circuit applies—after detecting the beginning of a data transmission—to the interface circuit a first clock signal which is required for the operation of the interface circuit, and wherein the control circuit interrupts—after detecting the end of a data transmission—the first clock signal which is required for the operation of the interface circuit, and wherein the control circuit is adapted to switch the first clock signal at the opposite slope of the decisive slope of the sampling stage of the interface circuit, whereby a fixed time is available before and after the data transmission for setting up and completing the transmission.
A method for controlling a data bus interface with a clock and a data line, in which interface receiving and transmitting circuitry samples the clock and data lines at a multiple of the data rate of the data bus interface, including the steps of:
Dependencies are inferred from the claim text.