Memory controller, bus system, integrated circuit, and control method of integrated circuit
AssigneeNEC Electronics Corporation
InventorHiroshi Morita
Life of this patent
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Abstract
An integrated circuit including: a bus system including a bus master connected to a bus; and a memory controller connected to the bus system and controlling a connection between the bus master and a memory, in which the bus system includes a counter counting a waiting time from a time the bus master outputs a memory access request until a time a connection between the bus master and the memory controller is established, and the memory controller controls a memory access based on the waiting time counted by the counter.
Claims17
An integrated circuit comprising:
- a bus system including a bus master connected to a bus;
- and
- a memory controller connected to the bus system, and controlling a connection between the bus master and a memory,
- wherein the bus system includes a counter counting a waiting time from a time the bus master outputs a memory access request until a time a connection between the bus master and the memory controller is established, and
- the memory controller controls a memory access based on the waiting time counted by the counter.
A bus system controlling a connection between a bus master and a memory and connected to a memory controller, the bus system comprising:
- a counter counting a waiting time from a time the bus master sends an access request, until a time a connection between the bus master and the memory controller is established.
A memory controller, connected to a bus system including a plurality of buses connected to a bus master, the memory controller comprising:
- a latency control timer receiving a waiting time counted by a counter;
- and
- an arbiter determining a priority order of the bus master to access the memory.
A control method of an integrated circuit including a bus system including a bus master connected to a bus and a memory controller connected to the bus system and controlling a connection between the bus master and a memory, the control method comprising:
- counting a waiting time from a time the bus master sends an access request for the memory, until a time the connection between the bus master and the memory controller is established;
- and
- controlling a memory access of the bus master based on the counted waiting time.
Dependencies are inferred from the claim text.