High data rate serial peripheral interface

A serial peripheral interface for use with a central processing unit (CPU);

• a bus interface in communication with the CPU;
• a CPU memory module in communication with the bus interface;
• the CPU memory module configured to include a FIFO memory buffer;
• and a direct memory access module in communication with the bus interface;
• comprising:
• the serial peripheral interface (SPI) in communication with the direct memory access module and the bus interface;
• the serial peripheral interface having SPI hardware configured to maintain pointers to addresses within the FIFO memory buffer;
• the SPI hardware configured to maintain counters;
• and
• the serial peripheral interface configured to use the FIFO memory buffer, pointers and counters as a transmission buffer for external communications for creating a virtual special function register.