Simulation device for co-verifying hardware and software

A simulation device for co-verifying hardware and software running on a target processor, the simulation device comprising:

• a scheduler managing an execution schedule for software under test and a hardware model describing hardware in a system-level design language;
• and
• a timer calculating a processing time of the software under test, based on a processing time that the simulation device has consumed to execute the software under test;
• wherein the scheduler delays starting a next simulation process, based on the calculated processing time.

A computer-readable medium a computer-executable program for co-verifying hardware and software running on a target processor, the computer-executable program causing a computer to function as a system comprising:

• a) a framework comprising:
• a first scheduler managing a first execution schedule for software under test, and
• a communication channel between the software under test and a hardware model describing hardware in a system-level design language;
• and
• b) a second scheduler managing a second execution schedule for the framework and the hardware model;
• wherein the framework further comprises an execution right manager that releases an execution right to the second scheduler in accordance with the first execution schedule for the software under test.