Interconnection process
AssigneeUnited Microelectronics Corp.
InventorsHong Ma, Shi-Jie Bai
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AssigneeUnited Microelectronics Corp.
InventorsHong Ma, Shi-Jie Bai
Estimating the term…
An interconnection process is described. A substrate having a conductive region formed therein is provided. A dielectric layer is formed on the substrate. A patterned metal hard mask layer having a trench opening is formed on the dielectric layer. A dielectric hard mask layer is formed conformally on the patterned metal hard mask layer and filled in the trench opening. A photoresist pattern is defined to remove a portion of the dielectric hard mask layer and a portion of the dielectric layer to form a first opening in the dielectric layer. The photoresist pattern is removed. A first etching process is performed using the patterned metal hard mask layer as a mask to form a trench and a second opening extending downward from the first opening in the dielectric layer. The second opening exposes the conductive region. A conductive layer is formed in the trench and the second opening.
An interconnection process, comprising:
11-21. (canceled)
Dependencies are inferred from the claim text.