Method of manufacturing a semiconductor device
AssigneeKabushiki Kaisha Toshiba
InventorMasaaki HATANO
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Abstract
A method of manufacturing a semiconductor device, includes forming a structure wherein a first alignment mark is provided in a first alignment-mark arrangement area of a first layer, a second alignment mark is provided in a second alignment-mark arrangement area of a second layer, a dummy pattern is provided above the first alignment-mark arrangement area, and substantially no dummy pattern is provided above the second alignment-mark arrangement area, and aligning a third layer provided above the structure by using the second alignment mark.
Claims20
A method of manufacturing a semiconductor device, comprising:
- forming a structure wherein a first alignment mark is provided in a first alignment-mark arrangement area of a first layer, a second alignment mark is provided in a second alignment-mark arrangement area of a second layer, a dummy pattern is provided above the first alignment-mark arrangement area, and substantially no dummy pattern is provided above the second alignment-mark arrangement area;
- and
- aligning a third layer provided above said structure by using the second alignment mark.
A method of manufacturing a semiconductor device, comprising:
- forming a structure wherein a pair of first overlay-accuracy measuring marks for measuring an overlay accuracy of patterns is provided in a first overlay-accuracy measuring mark pair arrangement area;
- and
- forming a dummy pattern above the first overlay-accuracy measuring mark pair arrangement area.
A method of manufacturing a semiconductor device, comprising:
- forming a structure wherein a first dimension-accuracy measuring mark for measuring a dimension-accuracy of a pattern is provided in a first dimension-accuracy measuring mark arrangement area;
- and
- forming a dummy pattern above the first dimension-accuracy measuring mark arrangement area.
Dependencies are inferred from the claim text.