Method of Producing Non Volatile Memory Device

A method of fabricating a semiconductor structure, the method comprising:

• depositing an insulator over a semiconductor body;
• depositing a conducting material over the insulator;
• using a lithography step to expose a portion of the conducting material;
• etching the exposed portion of the conducting material to expose a portion of the insulator, wherein the etching is performed in a reactive ion etch chamber using a first gas chemistry;
• physically damaging the exposed portion of the insulator, wherein the damage is performed in the reactive ion etch chamber using a second gas chemistry;
• and
• etching the damaged insulator.

A method for fabricating a semiconductor body comprising memory areas and logic areas, the memory areas comprising floating gate transistors and select gate transistors, the logic areas comprising field effect transistors, the method comprising:

• separating the semiconductor body into memory and logic areas, the memory areas further comprising of select gate and floating gate areas;
• depositing a first gate dielectric over the memory areas;
• depositing a first conducting material over the first gate dielectric;
• depositing an inter poly dielectric material over the first conducting material;
• depositing a second gate dielectric over the logic areas;
• depositing a second conducting material over the logic and memory areas;
• using a lithography step to expose a portion of the second conducting material over the logic and memory areas;
• etching the exposed portion of the second conducting material to expose a portion of the inter poly dielectric material on the memory areas and the second gate dielectric on the logic areas, wherein the etching is performed in a reactive ion etch chamber using a first gas chemistry;
• physically damaging the exposed portion of the inter poly dielectric material, wherein the damage is performed in the reactive ion etch chamber using a second gas chemistry;
• etching the damaged inter poly dielectric material to expose a portion of the first conducting material;
• etching the second gate dielectric to expose a portion of the semiconductor body in the logic regions;
• etching the exposed portion of the first conducting material to expose a portion of the first gate dielectric, wherein the etching is performed in the reactive ion etch chamber using a third gas chemistry;
• and
• etching the first gate dielectric to expose a portion of the semiconductor body in the memory regions.