DQPSK Transmitter With Parallel Precoder And High-Speed DQPSK Data Stream Realignment
AssigneeCiena Corporation
InventorsJohn Brownlee, Boris Kershteyn
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Abstract
The present invention utilizes field programmable gate arrays (FPGAs) to implement a parallel differential quadrature phase shift keying (DQPSK) precoder and a DQPSK optical transmitter with an automatic realignment process. The present invention can perform DQPSK preceding, modulation, and data stream realignment at any lower rate, and its upper rate is determined by capability in speed and logic resources and external connections of available integrated circuit technology.
Claims19
A parallel precoder circuit, comprising:
- preceding circuitry configured to process a first and second high-speed data stream;
- a first field programmable gate array comprising a first high-speed input/output interface configured to:
- receive the first high-speed data stream;
- process the first high-speed data stream to a lower rate;
- transmit the first high-speed data stream to the preceding circuitry;
- receive the processed first high-speed data stream;
- and
- transmit the processed first high-speed data stream to a first multiplexer;
- a second field programmable gate array comprising a second high-speed input/output interface configured to:
- receive the second high-speed data stream;
- process the second high-speed data stream to a lower rate;
- transmit the second high-speed data stream to the preceding circuitry;
- receive the processed second high-speed data stream;
- and
- transmit the processed second high-speed data stream to a second multiplexer;
- a clock unit configured to provide timing to the preceding circuitry, the first field programmable gate array, and the second field programmable gate array.
A Differential Quadrature Phase Shift Keying optical transmitter, comprising:
- a parallel precoder configured to receive a first and second high-speed data stream, and to encode and synchronize the first and second high-speed data stream for Differential Quadrature Phase Shift Keying modulation;
- an alignment circuit configured to receive the precoded first and second high-speed data stream streams from the parallel precoder;
- a first and second multiplexer, wherein the first multiplexer is configured to receive the first precoded high-speed data stream from the alignment circuit, and the second multiplexer is configured to receive the second precoded high-speed data stream from the alignment circuit;
- a first and second Differential Quadrature Phase Shift Keying modulator driver, wherein the first Differential Quadrature Phase Shift Keying modulator driver is configured to receive the first multiplexed high-speed data stream, and the second Differential Quadrature Phase Shift Keying modulator driver is configured to receive the second multiplexed high-speed data stream;
- and
- a Differential Quadrature Phase Shift Keying modulator configured to modulate an optical signal responsive to outputs from the first and second Differential Quadrature Phase Shift Keying modulator drivers;
- wherein the alignment circuit is configured to phase lock the first and second high-speed data streams.
A parallel precoding and high-speed data stream realignment method for a Differential Quadrature Phase Shift Keying optical transmitter, comprising:
- receiving a first and second high-speed data stream;
- processing the first and second high-speed data streams to a lower rate;
- encoding the first and second high-speed data streams;
- synchronizing the first and second high-speed data streams;
- serializing the first and second high-speed data streams;
- monitoring phase differences between the serialized first and second high-speed data streams;
- and
- adjusting one of the first and second high-speed data streams responsive to phase differences to achieve a phase lock between the serialized first and second high-speed data streams.
Dependencies are inferred from the claim text.