Systems and methods for efficient generation of hash values of varying bit widths
AssigneeFreescale Semiconductor, Inc.
InventorMichael J. Torla
Life of this patent
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Abstract
A technique for producing a hashed output of an input message according to any number of hash algorithms (e.g. SHA-256, SHA-348, SHA-512) having varying bit widths is described. At least a portion of the input message is stored in a first group of registers each having a bit width equal to a first bit width (e.g. 32 bits). If the selected hash algorithm has a larger bit width (e.g. 64 bits), a remainder of the input message is stored in a second plurality of registers each having a bit width equal to the first bit width. The hashed output is then computed according to the selected hash algorithm.
Claims20
A method for producing a hashed output of an input message according to any of a plurality of hash algorithms, each of the plurality of hash algorithms having an associated bit width such that at least one of the algorithms is associated with a first bit width and at least one of the algorithms is associated with a second bit width greater than the first bit width, the method comprising the steps of:
- receiving the input message and a selected one of the plurality of hash algorithms;
- storing at least a portion of the input message in a first plurality of registers each having a bit width equal to the first bit width;
- if the selected one of the plurality of hash algorithms is associated with the second bit width, storing a remainder of the input message in a second plurality of registers each having a bit width equal to the first bit width, and otherwise bypassing the second plurality of registers;
- and
- computing the hashed output according to the selected one of the plurality of hash algorithms.
A system for producing a hashed digest of an input message according to any of a plurality of hash algorithms, each of the plurality of hash algorithms having an associated bit width such that at least one of the algorithms is associated with a first bit width and at least one of the algorithms is associated with a second bit width greater than the first bit width, the system comprising:
- a first plurality of message registers each having a bit width corresponding to the first bit width;
- a second plurality of message registers having a bit width corresponding to the first bit width;
- control logic configured to receive the input message and a selected one of the plurality of hash algorithms, to store at least a portion of the input message in the first plurality of message registers and, if the selected one of the plurality of hash algorithms is associated with the second bit width, to store a remainder of the input message in the second plurality of message registers, and to compute the hashed output according to the selected one of the plurality of hash algorithms using only the first plurality of message registers if the selected hash algorithm is associated with the first bit width and using the first and second pluralities of message registers if the selected hash algorithm is associated with the second bit width.
A message digest hardware accelerator system configured to produce a hashed digest of an input message according to any of a plurality of hash algorithms, each of the plurality of hash algorithms having an associated bit width such that a first one of the algorithms is associated with a thirty-two bit width and a second one of the algorithms is associated with a sixty-four bit width, the message digest hardware accelerator system comprising:
- a first and a second plurality of thirty-two bit message registers;
- a first and a second plurality of thirty-two bit digest registers;
- and
- control logic configured to receive the input message and a selected one of the plurality of hash algorithms, to store at least a portion of the input message in the first plurality of message registers and to store a remainder of the input message in the second plurality of message registers if the selected one of the plurality of hash algorithms is a sixty-four bit algorithm, to compute the hashed output according to the selected one of the plurality of hash algorithms using only the first plurality of message registers and the first plurality of digest registers if the selected hash algorithm is a thirty-two bit algorithm and using the first and second pluralities of message registers and the first and second pluralities of digest registers if the selected hash algorithm is a sixty-four bit algorithm, and to process a carry between at least one of the first pluralities of registers and at least one of the second pluralities of registers during a bitwise operation of the sixty-four bit algorithm.
Dependencies are inferred from the claim text.