Integrated logic circuit and method for producing an integrated logic circuit
AssigneeQimonda AG
InventorJosef Hoelzle
Life of this patent
Estimating the term…
Abstract
An integrated logic circuit comprises a memory area, wherein the memory area comprises a plurality of groups of memory cells, each group of memory cells assigned an address. The memory area further comprises an address decoder having a plurality of address inputs for receiving an address and for selecting a group of memory cells to which the received address is assigned and a plurality of data outputs for outputting information stored in a group of memory cells which is selected by the address decoder. The integrated logic circuit further comprises a coupling device which couples at least one portion of the data outputs of the memory area to at least one portion of the address inputs of the address decoder.
Claims15
An integrated logic circuit, comprising:
- a memory area, wherein the memory area comprises:
- a plurality of groups of memory cells, wherein each group of memory cells is assigned an address;
- an address decoder having a plurality of address inputs for receiving an address and for selecting a group of memory cells to which the received address is assigned;
- and
- a plurality of data outputs for outputting information stored in a group of memory cells which is selected by the address decoder,
- wherein the integrated circuit further comprises a coupling device which couples at least one portion of the data outputs of the memory area to at least one portion of the address inputs of the address decoder.
An integrated component, comprising:
- a plurality of memory areas, wherein each memory area comprises a plurality of groups of memory cells which are each assigned an address;
- an address decoder having a plurality of address inputs for receiving an address in order to select a group of memory cells to which the received address is assigned;
- a plurality of data outputs for outputting information stored in the group of memory cells which is selected by the address decoder;
- and
- a coupling device which couples a first group of the data outputs of at least one first memory area to a first group of the address inputs of the address decoder of any of the at least one first memory area and of at least one second memory area, wherein memory cells of any of the first memory area and of the second memory area contain data which define a logic implemented in the component.
A method for producing an integrated logic circuit, comprising:
- producing a plurality of groups of memory cells;
- producing an address decoder having a plurality of address inputs for receiving an address and for selecting a group of memory cells to which the received address is assigned;
- producing a plurality of data outputs for outputting information stored in the group of memory cells which is selected by the address decoder;
- and
- producing a coupling device which couples at least one portion of the data outputs of the memory area to at least one portion of the address inputs of the address decoder.
A method for implementing a logic on an integrated component, comprising:
- providing a plurality of memory areas, wherein each memory area comprises a plurality of groups of memory cells which are in each case assigned an address;
- providing an address decoder having a plurality of address inputs for receiving an address in order to select a group of memory cells to which the received address is assigned;
- and
- providing a plurality of data outputs for outputting information stored in a group of memory cells which is selected by the address decoder, wherein a first group of the data outputs of at least one first memory area is coupled to a first group of the address inputs of the address decoder of any of the at least one first memory area and of at least one further second memory area, and wherein data which define a logic implemented in the component are stored in memory cells of any of the first memory area and of the further second memory area.
Dependencies are inferred from the claim text.