Apparatus and method of controlling bank of semiconductor memory
AssigneeHynix Semiconductor Inc.
InventorSeung-Wook Kwack
Life of this patent
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Abstract
An apparatus for controlling bank of a semiconductor memory includes a plurality of banks, a peripheral circuit unit that generates and outputs a bank selection signal and a first address, and a bank controller that generates a second address obtained by correcting the first address to match a bank control timing and outputs the generated second address to a bank corresponding to the bank selection signal among the plurality of banks. Since it is easy to ensure a timing margin, it is possible to completely prevent an address generation error, minimize a layout area, and reduce current consumption.
Claims11
An semiconductor memory apparatus, comprising:
- a bank controller configured to latch an present address until a new address is inputted thereby generating a latched address, and to provide the latched address to a bank corresponding to a bank selection signal.
An apparatus for controlling a bank of a semiconductor memory apparatus, comprising:
- a plurality of bank areas, each of which has a plurality of banks;
- a peripheral circuit unit configured to generate and output a bank selection signal and a first address;
- a plurality of bank controllers, each of which is configured to generate a second address by latching the first address to match a bank control timing and provide the second address to a bank corresponding to the bank selection signal;
- and
- a plurality of column controllers, each of which is configured to control the input and output of data of the bank according to the second address.
Dependencies are inferred from the claim text.