Charge recycling method and driving circuit and low power memory using the same

A driving circuit for a memory, comprising:

• a first switch having a first terminal coupled to a first voltage;
• a first driver, which comprises:
• a second switch having a first terminal coupled to a second terminal of the first switch, and a second terminal coupled to a first capacitor;
• and
• a third switch having a first terminal coupled to the second terminal of the second switch, and a second terminal coupled to a second voltage;
• and
• a second driver, which comprises:
• a fourth switch having a first terminal coupled to the second terminal of the first switch, and a second terminal coupled to a second capacitor;
• and
• a fifth switch having a first terminal coupled to the second terminal of the fourth switch, and a second terminal coupled to the second voltage.

A memory, comprising:

• a plurality of bit lines;
• a memory cell array coupled to the bit lines;
• a Y multiplexer having a plurality of select transistors arranged in an array, first terminals of the select transistors being respectively coupled to the bit lines;
• a Y pre-decode driving circuit, which comprises:
• a first switch having a first terminal coupled to a first voltage;
• and
• a plurality of pre-decode drivers, each of which is for controlling one row of the select transistors and comprises:
• a second switch having a first terminal coupled to a second terminal of the first switch, and a second terminal coupled to the row of the select transistors;
• and
• a third switch having a first terminal coupled to the second terminal of the second switch, and a second terminal coupled to a second voltage;
• and
• a bit line driving unit, which is coupled to second terminals of the select transistors, and selects a desired one of the bit lines in cooperation with the pre-decode drivers.

A memory, comprising:

• a plurality of word lines and bit lines;
• a memory cell array coupled to the word lines and the bit lines;
• a bit line driving unit for selecting a desired one of the bit lines;
• and
• an X decoder, which comprises:
• a first switch having a first terminal coupled to a first voltage;
• and
• a plurality of pre-decode drivers, each of which is for controlling one of the word lines and comprises:
• a second switch having a first terminal coupled to a second terminal of the first switch, and a second terminal coupled to the corresponding word line;
• and
• a third switch having a first terminal coupled to the second terminal of the second switch, and a second terminal coupled to a second voltage.

A driving method applied in a driving circuit for a memory having a first load and a second load, the method comprising the steps of:

• charging the first load to a high voltage;
• turning off charging the first load;
• sharing charges from the first load to the second load after said turning off charging the first load;
• and
• charging the second load to the high voltage.