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US 2009/0022003 A1Published application
Memory cell structures, memory arrays, memory devices, memory controllers, and memory systems, and methods of manufacturing and operating the same
AssigneeSamsung Electronics Co., Ltd.
InventorsKi-Whan SONG, Nam-Kyun Tak
Life of this patent
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Abstract
Example embodiments are directed to memory cell structures, memory arrays, memory devices, memory controllers, and memory systems using bipolar junction transistor (BJT) operation.
Claims56
A memory device, comprising:
- a memory array including a plurality of memory cells, each memory cell including a floating body transistor having a first node, a second node, and a gate node, connected to at least one bit line, at least one source line and at least one word line, respectively;
- and
- a control unit for performing a refresh operation in response to a refresh command by selecting one of the at least one source line and the at least one bit line, wherein if first data is stored at a memory cell connected to the selected line, a first current caused by bipolar junction operation flows.
A memory device, comprising:
- a memory array including a plurality of memory cells, each memory cell including a floating body transistor having a first node, a second node, and a gate node, connected to at least one bit line, at least one source line and at least one word line, respectively;
- and
- a control unit for performing a write operation by applying a bit line write voltage to the at least one bit line according to data information, then applying a source line write voltage to the at least one source line, and then applying a word line write voltage to the at least one word line.
A memory cell structure, comprising:
- a silicon-on-insulator structure including a substrate, an insulator, and a silicon layer, the silicon layer including first and second nodes doped with impurities, a floating body region, and a buffer region between one of the first and second nodes and the floating body, wherein the buffer region has a lower impurity concentration that the adjacent node or the floating body and wherein the buffer region covers the entire boundary of the one of the first and second nodes;
- and
- a gate structure on the silicon layer.
A memory cell structure, comprising:
- a silicon-on-insulator structure including a substrate, an insulator, and a silicon layer, the silicon layer including first and second nodes doped with impurities, a floating body region having a floating body length therebetween, and a buffer region between one of the first and second nodes and the floating body, wherein the buffer region has a lower impurity concentration that the adjacent node or the floating body;
- and
- a gate structure having a gate length on the silicon layer, wherein the floating body length is greater than the gate length.
A memory cell structure, comprising:
- a silicon-on-insulator structure including a substrate, an insulator, and a silicon layer, the silicon layer including an emitter/source and a collector/drain doped with impurities, a floating body region, and an auxiliary body region between the emitter/source and the floating body, wherein the auxiliary body region has a lower impurity concentration than that of the floating body;
- and
- a gate structure on the silicon layer.
A memory cell structure, comprising:
- a silicon-on-insulator structure including a substrate, an insulator, and a silicon layer, the silicon layer including first and second nodes doped with impurities, a floating body region, and an extended body region adjacent to the floating body region;
- and
- a gate structure on the silicon layer.
A memory cell structure, comprising:
- an insulating layer on a substrate;
- a silicon pattern on the insulating layer and including a first node, second node and a floating body region;
- and
- a gate surrounding the floating body region,
- wherein the length of the gate is less than the floating body region and wherein a voltage difference between voltages applied to the first and second nodes for a given voltage applied to the gate induces a bipolar junction operation.
2 more elements
A memory cell structure, comprising:
- an insulating layer on a substrate;
- a silicon pattern on the insulating layer, which including a first node, second node and a floating body region;
- an extended body region on the floating body region;
- and
- a gate structure surrounding the floating body region and the extended body region.
2 more elements
A method for controlling a refresh operation of a memory device including a plurality of capacitor-less memory cells, comprising:
- providing a mode register set command for identifying one of a block refresh operation and a partial refresh operation for the memory device;
- and
- providing a refresh command for the refresh operation.
A memory controller, comprising:
- a first register storing a mode register set command for selecting one of block refresh and a partial refresh for a memory device.
A capacitor-less memory device, comprising:
- a first register storing information of a refresh operation for selecting one of a block refresh and a partial refresh.
A memory cell structure, comprising:
- a silicon-on-insulator structure including a substrate, an insulator, and a silicon layer, the silicon layer including first and second nodes, a floating body region;
- and
- a gate on the floating body region,
- wherein the length of gate is less than the length of the floating body, and wherein a difference between voltages applied to the first and second nodes for a given voltage applied to the gate induces a bipolar junction operation.
1 more element
A memory device, comprising:
- a memory array including a plurality of memory cells, each memory cell including a floating body transistor having a first node, a second node and a gate, connected to at least one bit line, at least one source line and at least one word line, respectively;
- and
- a control unit for performing a read operation by selecting one of the at least one source line and by not selecting any of the at least one word lines, wherein if first data is stored at a memory cell connected to the selected source line, a first current caused by bipolar junction operation flows.
Dependencies are inferred from the claim text.