Semiconductor memory device

A semiconductor memory device including a memory array portion having a plurality of memory cells (MC) arranged in a matrix, charge line (CL), word line (WL) and bit lines (BL), in which each of said plurality of memory cells has an access transistor (ATr) and a storage transistor (STr) connected in series between said one of bit lines (BL) and said power source potential (VDD),

• the gate of said storage transistor (STr) is connected to said charge line (CL) and the gate of said access transistor (ATr) is connected to said word line (WL),
• said storage transistor (STr) and said access transistor (ATr) are isolated electrically from other adjoining memory cells (MC),
• by switching the potential of a connection node of said storage transistor (STr) and said access transistor (ATr) to a constant potential or a floating condition by turning ON/OFF said access transistor (ATr), the potential of a body region (23b) of said storage transistor (STr) is set to a high level or a low level so as to memorize binary data,
• wherein by activating said word line (WL) and said one of bit lines (BL) in parallel with said storage transistor (STr) set to OFF, the potential conditions of said charge line (CL), said word line (WL) and said one of bit lines (BL) are controlled so that the potential of said body region (23b) is raised by a leak current flowing from a drain side toward said body region (23b) in a period until said storage transistor (STr) is turned ON.

A semiconductor memory device including a memory array portion having a plurality of memory cells (MC) arranged in a matrix, charge line (CL), word line (WL) and bit lines (BL), in which each of the plurality of said memory cells has an access transistor (ATr) and a storage transistor (STr) connected in series between said one of bit lines (BL) and the power source potential (VDD),

• the gate of said storage transistor (STr) is connected to said charge line (CL) and the gate of said access transistor (ATr) is connected to said word line (WL),
• said storage transistor (STr) and said access transistor (ATr) are isolated electrically from adjoining other memory cells (MC),
• by switching the potential of a connection node of said storage transistor (STr) and said access transistor (ATr) to a constant potential or a floating condition by turning ON/OFF said access transistor (ATr), the potential of a body region (23b) of said storage transistor (STr) is set to a high level or a low level so as to memorize binary data,
• wherein,
• said bit line (BL) is disposed such that a first bit line (BL) and a second bit line (/BL) make a pair,
• said plurality of memory cells (MC) include
• a first memory cell in which said access transistor (ATr) is connected to said first bit line (BL), and
• a second memory cell in which said access transistor (ATr) is connected to said second bit line (/BL),
• said memory array portion includes
• a first reference potential applying means for providing a reference potential to said first bit line (BL) and
• a second reference potential applying means for providing reference potential to said second bit line (/BL),
• said semiconductor memory device further comprising
• a program unit (6) which programs a combination of signals to be provided to control lines (DWL0, DWL1) of said charge line (CL), said word line (WL), and the first and second reference potential applying means and uses the plurality of said memory cells (MC) as a 1-bit 2-cell type memory cells for memorizing 1-bit information with two memory cells or 1-bit 1-cell type memory cells for memorizing 1-bit information with a memory cell.