US 2009/0022000 A1Published application

Semiconductor storage device and test method therefor

AssigneeNEC Electronics Corporation

InventorTakayoshi Sannomiya

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Abstract

Disclosed is a semiconductor device including a BIST provided with a plurality of scan FFs (flip-flops), a data address signal generation circuit unit which respectively generates a data signal and an address signal based on a set value of a scan FF, WEB generation circuit unit which generates a signal WEB which controls writing to and reading data from the semiconductor memory based on an scan FF value, and a test signal control circuit unit which controls the data address signal generation circuit unit and the WEB generation circuit unit, based on a received control signal, controls selectors, and selects and controls, as data and address signals to be supplied to the memory, data signal and address signals from the data address signal generation circuit unit or data and address signals via a user defined circuit.

Claims14

Dependent claims

A semiconductor device comprising:

a BIST (Built in Self Test) that includes a plurality of scan flip-flops which are able to be serially connected and are respectively set to any value of 0 and 1 by a scan-shift operation;
a data address signal generation circuit unit that generates a data signal based on a set value of a first scan flip-flop in said BIST, and that generates an address signal based on a set value of a second scan flip-flop in said BIST;
a write/read signal generation circuit unit that generates a signal controlling writing to and reading from an electronically writable and readable memory, and supplies the generated signal to said memory;
and
a test signal control circuit unit that controls said data address signal generation circuit unit and said write/read signal generation circuit unit, based on a control signal received, and that selects, as a data signal and/or an address signal to be supplied to said memory, a data signal and/or an address signal from said data address signal generation circuit unit.

2 more elements

Dependencies are inferred from the claim text.