Semiconductor device
AssigneeElpida Memory, Inc.
InventorsNaoya TANIMURA, Tomohiko SATO, Chiaki DONO
Life of this patent
Estimating the term…
Abstract
Disclosed is a semiconductor storage device in which a cell array including a plurality of cells in need of refresh for data retention includes the redundancy area, which has a plurality of redundant cells for replacing faulty cells of a normal area within the cell array. When the redundancy area is tested, a refresh counter circuit for generating and outputting refresh addresses rearranges the address in such a manner that a row address of the redundancy area is substantially reduced and placed on a lower-order bit side inclusive of the LSB of the counter.
Claims10
A semiconductor storage device comprising:
- a cell array that includes a plurality of cells in a normal area and a plurality of redundant cells in a redundancy area for replacing faulty cells in the normal area, the cells being in need of refresh for data retention;
- and
- a refresh counter circuit that generates and outputs a refresh address for the cell array, the refresh counter circuit rearranging a bit arrangement of a count output thereof, when the redundancy area is subjected to a test, in such a manner that a refresh address for the redundancy area is reduced and placed on neighboring lower-order bits inclusive of the least significant bit (LSB) of a count-output of the refresh counter circuit.
A semiconductor storage device comprising:
- a memory cell array including a normal memory cell area and a redundant memory cell area;
- a refresh counter producing refresh address information, the refresh address information including a first address part having at least one first bit, a second address part having at least one second bit that is more significant than the first bit, and a third address part having at least one third bit that is more significant than the second bit;
- and
- an access circuit receiving the refresh address information and operating in a first mode to access the memory cell array with making the second part more significant than each of the first and third address parts and in a second mode to access the redundant memory cell area with making the first address part more significant than the second part and without using the third address part.
A semiconductor storage device comprising:
- a plurality of memory blocks, each of the memory blocks having a plurality of memory mats, each of the memory mats including a plurality of normal memory areas and a redundant memory area, each of the normal memory areas including a plurality of normal memory cells and a plurality of word lines, and the redundant memory area including a plurality of redundant memory cells and a plurality of redundant word lines;
- an address decoder circuit making an access to the memory cell array in response to address information, the address information including a first address part designating one of the memory blocks, a second address part designating one of the memory mats, a third address part designating one of normal memory areas and at least one of the normal word lines of the one of the normal memory areas;
- a refresh counter generating refresh address information, the refresh address information being changed in bit sequence from the least significant bit to the most significant bit, the refresh address information including a fourth address part inclusive of the least significant bit, a fifth address part inclusive of at least one more significant bit than the fourth address part, and a sixth address part inclusive of at least one more significant bit than the fifth address part, the fourth address part corresponding to a portion of the third address part, the fifth address portion corresponding to the second address part, and the sixth address part corresponding to a remaining portion of the third address part;
- and
- a test circuit activated in a test mode to perform a test operation on the redundant memory area in response to the refresh address information.
Dependencies are inferred from the claim text.