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US 2009/0021997 A1Published application
Methods and apparatus for improved write characteristics in a low voltage sram
AssigneeSony Computer Entertainment Inc.
InventorShunsaku Tokito
Life of this patent
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Abstract
Methods and apparatus provide for writing data into and reading data from an anti-parallel storage circuit of an SRAM memory cell via a true bit line (BLT) and a complementary bit line (BLC); and preventing the complementary bit line (BLC) from substantially dropping from a pre-charge, logic high voltage level during operations in which a logic low level is written into the anti-parallel storage circuit.
Claims10
An SRAM cell, comprising:
- an anti-parallel storage circuit operable to store a logic high or low value across a true node and a complementary node, where the true node and complementary node are coupled to a true bit line (BLT) and a complementary bit line (BLC), respectively;
- a write driver circuit operable to receive a write true WT input and a write complement WC input, and produce drive signals to the BLC and BLT lines;
- and
- a BLC driver operable to receive the WC input and produce a drive signal to push the BLC line to a logic high level in response to the WC input indicating that a logic low level is being written into the anti-parallel storage circuit,
- wherein the drive signal from the BLC driver is separate from the write driver circuit.
2 more elements
An SRAM memory, comprising:
- at least two memory cells, each including:
- (i) an anti-parallel storage circuit operable to store a logic high or low value across a true node and a complementary node, where the true node and complementary node are coupled to a true bit line (BLT) and a complementary bit line (BLC), respectively, and (ii) a write driver circuit operable to receive a write true WT input and a write complement WC input, and produce drive signals to the BLC and BLT lines;
- and
- a BLC driver operable to receive the WC input and produce respective drive signals to push the respective BLC lines to a logic high level in response to the WC input indicating that a logic low level is being written into the anti-parallel storage circuits,
- wherein the drive signals from the BLC driver is separate from the write driver circuits.
2 more elements
A method, comprising:
- writing data into and reading data from an anti-parallel storage circuit of an SRAM memory cell via a true bit line (BLT) and a complementary bit line (BLC);
- and
- preventing the complementary bit line (BLC) from substantially dropping from a pre-charge, logic high voltage level during operations in which a logic low level is written into the anti-parallel storage circuit.
Dependencies are inferred from the claim text.