Memory Circuit, Memory Component, Data Processing System and Method of Testing a Memory Circuit
OwnerMartin Versen, Helmut Schneiderinventors
Life of this patent
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Abstract
A memory circuit includes a plurality of bit lines and a plurality of memory cells which may be written to via a respective bit line. The memory circuit further includes a bit line control circuit. The bit line control circuit is configured to write, in a bit line-selective manner, a weak value to a memory cell coupled to a bit line selected.
Claims30
A memory circuit comprising:
- a plurality of bit lines;
- a plurality of memory cells writable via a respective bit line;
- and
- a bit line control circuit,
- the bit line control circuit being configured to write, in a bit line-selective manner, a weak value to a memory cell coupled to a bit line selected.
A memory module comprising a memory circuit, the memory circuit comprising:
- a plurality of bit lines;
- a plurality of memory cells writable via a respective bit line;
- and
- a bit line control circuit,
- the bit line control circuit being configured to write, in a bit line-selective manner, a weak value to a memory cell coupled to a bit line selected.
A data processing system, comprising:
- a processor;
- and
- a memory module comprising a memory circuit comprising:
- a plurality of bit lines;
- a plurality of memory cells writable via a respective bit line;
- and
- a bit line control circuit,
- the bit line control circuit being configured to write, in a bit line-selective manner, a weak value to a memory cell coupled to a bit line selected;
- the processor being coupled to the memory module to read out data from the memory module or to write data to the memory module.
A memory circuit comprising:
- a plurality of means for storing data;
- a plurality of means for connecting the means for storing data to associated means for reading out data;
- and
- means for selective writing of a weak value to a means for storing which is coupled to a selected means for connecting.
A method for testing a memory circuit comprising a plurality of bit lines and a plurality of memory cells, the memory cells being writable via a respective bit line, and the method comprising:
- bit line-selective writing of a weak value to a memory cell to be tested of the memory circuit;
- and
- testing the memory cell to which the weak value has been written.
A memory circuit, comprising:
- a plurality of bit lines;
- a plurality of memory cells writable via a respective bit line;
- a bit line control circuit adapted to write, in a bit line-selective manner, a weak value to a memory cell coupled to a bit line selected;
- and
- a primary sense amplifier adapted to amplify a potential difference existing between two bit lines coupled to the primary sense amplifier;
- wherein the bit line control circuit comprises a bit line driver adapted to drive, in a bit line-selective manner, a bit line to three different voltage levels as a function of a control signal;
- the bit line control circuit being adapted to adjust the bit line driver such that the bit line driver drives a weak write level to the bit line selected during writing of a weak value;
- and
- the bit line control circuit being adapted to deactivate the primary sense amplifier, or to leave it deactivated, during writing of a weak value.
Dependencies are inferred from the claim text.