Semiconductor memory device

A semiconductor memory device comprising:

• a memory cell array including a plurality of memory cells;
• a data access circuit performing a data access operation on at least one of the memory cells which is designated by first address information and second address information;
• and
• a control circuit operating in a first mode to supply the data access circuit with a first address, which accompanies a first command, as the first address information and with a second address, which accompanies a second command appearing subsequently to the first command, as the second address information, the control circuit further operating in a second mode to supply the data access circuit with a third address, which accompanies a third command appearing prior to the first command, as the first address information and with a fourth address, which accompanies the first command, as the second address information.

A method of performing one of data read and write operations on a semiconductor memory device, comprising:

• supplying, in a first mode, a first command accompanying a first address and then a second command accompanying a second address;
• selecting, in the first mode, first memory cell or cells in response to the first and second addresses;
• performing one of the data read and write operations on the first memory cell or cells in response to the second command;
• supplying, in a second mode, a third command accompanying a third address and then the first command, followed by the second command accompanying a further address;
• selecting, in the second mode, second memory cell or cells in response to the third and fourth addresses;
• and
• performing one of the data read and write operations on the second memory cell or cells in response to the second command.